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Topics | Data Structures | Macros
System Control Block (SCB)
Defines and Type Definitions » Status and Control Registers » Nested Vectored Interrupt Controller (NVIC)

Type definitions for the System Control Block Registers. More...

Topics

 System Controls not in SCB (SCnSCB)
 Type definitions for the System Control and ID Register not in the SCB.
 
 Implementation Control Block register (ICB)
 Type definitions for the Implementation Control Block Register.
 

Data Structures

struct  SCB_Type
 Structure type to access the System Control Block (SCB). More...
 
struct  EMSS_Type
 

Macros

#define TPI_ACPR_SWOSCALER_Pos   0U
 
#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
 
#define TPI_PSCR_PSCount_Pos   0U
 
#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
 
#define TPI_LSR_nTT_Pos   1U
 
#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
 
#define TPI_LSR_SLK_Pos   1U
 
#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
 
#define TPI_LSR_SLI_Pos   0U
 
#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
 
#define TPI_ACPR_SWOSCALER_Pos   0U
 
#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
 
#define TPI_PSCR_PSCount_Pos   0U
 
#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
 
#define TPI_LSR_nTT_Pos   1U
 
#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
 
#define TPI_LSR_SLK_Pos   1U
 
#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
 
#define TPI_LSR_SLI_Pos   0U
 
#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
 
#define TPI_ACPR_SWOSCALER_Pos   0U
 
#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
 
#define TPI_FFCR_EnFmt_Pos   0U
 
#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
 
#define TPI_PSCR_PSCount_Pos   0U
 
#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
 
#define TPI_LSR_nTT_Pos   1U
 
#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
 
#define TPI_LSR_SLK_Pos   1U
 
#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
 
#define TPI_LSR_SLI_Pos   0U
 
#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define MPU_RLAR_PXN_Pos   4U
 
#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)
 
#define MPU_RBAR_ADDR_Pos   5U
 
#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DHCSR_S_FPD_Pos   23U
 
#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
 
#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
 
#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
 
#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
 
#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
 
#define CoreDebug_DHCSR_S_SDE_Pos   20U
 
#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
 
#define CoreDebug_DHCSR_C_PMOV_Pos   6U
 
#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
 
#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
 
#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
 
#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_S_FPD_Pos   23U
 
#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)
 
#define DCB_DHCSR_S_SUIDE_Pos   22U
 
#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
 
#define DCB_DHCSR_S_NSUIDE_Pos   21U
 
#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
 
#define DCB_DHCSR_C_PMOV_Pos   6U
 
#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)
 
#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
 
#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
 
#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
 
#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
 
#define DCB_DAUTHCTRL_UIDEN_Pos   10U
 
#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
 
#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
 
#define DCB_DAUTHCTRL_FSDMA_Pos   8U
 
#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
 
#define DIB_DAUTHSTATUS_SUNID_Pos   22U
 
#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )
 
#define DIB_DAUTHSTATUS_SUID_Pos   20U
 
#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )
 
#define DIB_DAUTHSTATUS_NSUNID_Pos   18U
 
#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )
 
#define DIB_DAUTHSTATUS_NSUID_Pos   16U
 
#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )
 
#define MEMSYSCTL_BASE   (0xE001E000UL)
 
#define ERRBNK_BASE   (0xE001E100UL)
 
#define PWRMODCTL_BASE   (0xE001E300UL)
 
#define EWIC_BASE   (0xE001E400UL)
 
#define PRCCFGINF_BASE   (0xE001E700UL)
 
#define ICB   ((ICB_Type *) SCS_BASE )
 
#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )
 
#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )
 
#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )
 
#define EWIC   ((EWIC_Type *) EWIC_BASE )
 
#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )
 
#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U
 
#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)
 
#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U
 
#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_Pos   14U
 
#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U
 
#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)
 
#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U
 
#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)
 
#define ICB_ACTLR_DISNWAMODE_Pos   11U
 
#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)
 
#define ICB_ACTLR_FPEXCODIS_Pos   10U
 
#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)
 
#define ICB_ICTR_INTLINESNUM_Pos   0U
 
#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)
 
#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U
 
#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)
 
#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U
 
#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)
 
#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U
 
#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U
 
#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)
 
#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U
 
#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)
 
#define MEMSYSCTL_MSCR_ECCEN_Pos   1U
 
#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)
 
#define MEMSYSCTL_PFCR_DIS_NLP_Pos   7U
 
#define MEMSYSCTL_PFCR_DIS_NLP_Msk   (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)
 
#define MEMSYSCTL_PFCR_ENABLE_Pos   0U
 
#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)
 
#define MEMSYSCTL_ITCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)
 
#define MEMSYSCTL_ITCMCR_EN_Pos   0U
 
#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)
 
#define MEMSYSCTL_DTCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)
 
#define MEMSYSCTL_DTCMCR_EN_Pos   0U
 
#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)
 
#define MEMSYSCTL_PAHBCR_SZ_Pos   1U
 
#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)
 
#define MEMSYSCTL_PAHBCR_EN_Pos   0U
 
#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)
 
#define EWIC_EVENTSPR_EDBGREQ_Pos   2U
 
#define EWIC_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)
 
#define EWIC_EVENTSPR_NMI_Pos   1U
 
#define EWIC_EVENTSPR_NMI_Msk   (0x1UL << EWIC_EVENTSPR_NMI_Pos)
 
#define EWIC_EVENTSPR_EVENT_Pos   0U
 
#define EWIC_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/)
 
#define EWIC_EVENTMASKA_EDBGREQ_Pos   2U
 
#define EWIC_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)
 
#define EWIC_EVENTMASKA_NMI_Pos   1U
 
#define EWIC_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_EVENTMASKA_NMI_Pos)
 
#define EWIC_EVENTMASKA_EVENT_Pos   0U
 
#define EWIC_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/)
 
#define EWIC_EVENTMASK_IRQ_Pos   0U
 
#define EWIC_EVENTMASK_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/)
 
#define ERRBNK_IEBR0_SWDEF_Pos   30U
 
#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)
 
#define ERRBNK_IEBR0_BANK_Pos   16U
 
#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)
 
#define ERRBNK_IEBR0_LOCATION_Pos   2U
 
#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)
 
#define ERRBNK_IEBR0_LOCKED_Pos   1U
 
#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)
 
#define ERRBNK_IEBR0_VALID_Pos   0U
 
#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)
 
#define ERRBNK_IEBR1_SWDEF_Pos   30U
 
#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)
 
#define ERRBNK_IEBR1_BANK_Pos   16U
 
#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)
 
#define ERRBNK_IEBR1_LOCATION_Pos   2U
 
#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)
 
#define ERRBNK_IEBR1_LOCKED_Pos   1U
 
#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)
 
#define ERRBNK_IEBR1_VALID_Pos   0U
 
#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)
 
#define ERRBNK_DEBR0_SWDEF_Pos   30U
 
#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)
 
#define ERRBNK_DEBR0_TYPE_Pos   17U
 
#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)
 
#define ERRBNK_DEBR0_BANK_Pos   16U
 
#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)
 
#define ERRBNK_DEBR0_LOCATION_Pos   2U
 
#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)
 
#define ERRBNK_DEBR0_LOCKED_Pos   1U
 
#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)
 
#define ERRBNK_DEBR0_VALID_Pos   0U
 
#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)
 
#define ERRBNK_DEBR1_SWDEF_Pos   30U
 
#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)
 
#define ERRBNK_DEBR1_TYPE_Pos   17U
 
#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)
 
#define ERRBNK_DEBR1_BANK_Pos   16U
 
#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)
 
#define ERRBNK_DEBR1_LOCATION_Pos   2U
 
#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)
 
#define ERRBNK_DEBR1_LOCKED_Pos   1U
 
#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)
 
#define ERRBNK_DEBR1_VALID_Pos   0U
 
#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)
 
#define ERRBNK_TEBR0_SWDEF_Pos   30U
 
#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)
 
#define ERRBNK_TEBR0_POISON_Pos   28U
 
#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)
 
#define ERRBNK_TEBR0_TYPE_Pos   27U
 
#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)
 
#define ERRBNK_TEBR0_BANK_Pos   24U
 
#define ERRBNK_TEBR0_BANK_Msk   (0x3UL << ERRBNK_TEBR0_BANK_Pos)
 
#define ERRBNK_TEBR0_LOCATION_Pos   2U
 
#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)
 
#define ERRBNK_TEBR0_LOCKED_Pos   1U
 
#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)
 
#define ERRBNK_TEBR0_VALID_Pos   0U
 
#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)
 
#define ERRBNK_TEBR1_SWDEF_Pos   30U
 
#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)
 
#define ERRBNK_TEBR1_POISON_Pos   28U
 
#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)
 
#define ERRBNK_TEBR1_TYPE_Pos   27U
 
#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)
 
#define ERRBNK_TEBR1_BANK_Pos   24U
 
#define ERRBNK_TEBR1_BANK_Msk   (0x3UL << ERRBNK_TEBR1_BANK_Pos)
 
#define ERRBNK_TEBR1_LOCATION_Pos   2U
 
#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)
 
#define ERRBNK_TEBR1_LOCKED_Pos   1U
 
#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)
 
#define ERRBNK_TEBR1_VALID_Pos   0U
 
#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_NMIPENDSET_Pos   31U
 
#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_CPUID_IMPLEMENTER_Pos   24U
 
#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 
#define SCB_CPUID_VARIANT_Pos   20U
 
#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)
 
#define SCB_CPUID_ARCHITECTURE_Pos   16U
 
#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 
#define SCB_CPUID_PARTNO_Pos   4U
 
#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 
#define SCB_CPUID_REVISION_Pos   0U
 
#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
 
#define SCB_ICSR_PENDNMISET_Pos   31U
 
#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)
 
#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos
 
#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk
 
#define SCB_ICSR_PENDNMICLR_Pos   30U
 
#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)
 
#define SCB_ICSR_PENDSVSET_Pos   28U
 
#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)
 
#define SCB_ICSR_PENDSVCLR_Pos   27U
 
#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)
 
#define SCB_ICSR_PENDSTSET_Pos   26U
 
#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)
 
#define SCB_ICSR_PENDSTCLR_Pos   25U
 
#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)
 
#define SCB_ICSR_STTNS_Pos   24U
 
#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)
 
#define SCB_ICSR_ISRPREEMPT_Pos   23U
 
#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 
#define SCB_ICSR_ISRPENDING_Pos   22U
 
#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)
 
#define SCB_ICSR_VECTPENDING_Pos   12U
 
#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 
#define SCB_ICSR_RETTOBASE_Pos   11U
 
#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)
 
#define SCB_ICSR_VECTACTIVE_Pos   0U
 
#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
 
#define SCB_VTOR_TBLOFF_Pos   7U
 
#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 
#define SCB_AIRCR_VECTKEY_Pos   16U
 
#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 
#define SCB_AIRCR_VECTKEYSTAT_Pos   16U
 
#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 
#define SCB_AIRCR_ENDIANESS_Pos   15U
 
#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)
 
#define SCB_AIRCR_PRIS_Pos   14U
 
#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)
 
#define SCB_AIRCR_BFHFNMINS_Pos   13U
 
#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)
 
#define SCB_AIRCR_PRIGROUP_Pos   8U
 
#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)
 
#define SCB_AIRCR_SYSRESETREQS_Pos   3U
 
#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
 
#define SCB_AIRCR_SYSRESETREQ_Pos   2U
 
#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 
#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U
 
#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 
#define SCB_SCR_SEVONPEND_Pos   4U
 
#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)
 
#define SCB_SCR_SLEEPDEEPS_Pos   3U
 
#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)
 
#define SCB_SCR_SLEEPDEEP_Pos   2U
 
#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)
 
#define SCB_SCR_SLEEPONEXIT_Pos   1U
 
#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 
#define SCB_CCR_BP_Pos   18U
 
#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)
 
#define SCB_CCR_IC_Pos   17U
 
#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)
 
#define SCB_CCR_DC_Pos   16U
 
#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)
 
#define SCB_CCR_STKOFHFNMIGN_Pos   10U
 
#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
 
#define SCB_CCR_BFHFNMIGN_Pos   8U
 
#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)
 
#define SCB_CCR_DIV_0_TRP_Pos   4U
 
#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)
 
#define SCB_CCR_UNALIGN_TRP_Pos   3U
 
#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 
#define SCB_CCR_USERSETMPEND_Pos   1U
 
#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)
 
#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U
 
#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U
 
#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
 
#define SCB_SHCSR_SECUREFAULTENA_Pos   19U
 
#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
 
#define SCB_SHCSR_USGFAULTENA_Pos   18U
 
#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 
#define SCB_SHCSR_BUSFAULTENA_Pos   17U
 
#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 
#define SCB_SHCSR_MEMFAULTENA_Pos   16U
 
#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 
#define SCB_SHCSR_SVCALLPENDED_Pos   15U
 
#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 
#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U
 
#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 
#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U
 
#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 
#define SCB_SHCSR_USGFAULTPENDED_Pos   12U
 
#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 
#define SCB_SHCSR_SYSTICKACT_Pos   11U
 
#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 
#define SCB_SHCSR_PENDSVACT_Pos   10U
 
#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)
 
#define SCB_SHCSR_MONITORACT_Pos   8U
 
#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)
 
#define SCB_SHCSR_SVCALLACT_Pos   7U
 
#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)
 
#define SCB_SHCSR_NMIACT_Pos   5U
 
#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)
 
#define SCB_SHCSR_SECUREFAULTACT_Pos   4U
 
#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
 
#define SCB_SHCSR_USGFAULTACT_Pos   3U
 
#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 
#define SCB_SHCSR_HARDFAULTACT_Pos   2U
 
#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
 
#define SCB_SHCSR_BUSFAULTACT_Pos   1U
 
#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 
#define SCB_SHCSR_MEMFAULTACT_Pos   0U
 
#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
 
#define SCB_CFSR_USGFAULTSR_Pos   16U
 
#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 
#define SCB_CFSR_BUSFAULTSR_Pos   8U
 
#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 
#define SCB_CFSR_MEMFAULTSR_Pos   0U
 
#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)
 
#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)
 
#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_HFSR_DEBUGEVT_Pos   31U
 
#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)
 
#define SCB_HFSR_FORCED_Pos   30U
 
#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)
 
#define SCB_HFSR_VECTTBL_Pos   1U
 
#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)
 
#define SCB_DFSR_EXTERNAL_Pos   4U
 
#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)
 
#define SCB_DFSR_VCATCH_Pos   3U
 
#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)
 
#define SCB_DFSR_DWTTRAP_Pos   2U
 
#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)
 
#define SCB_DFSR_BKPT_Pos   1U
 
#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)
 
#define SCB_DFSR_HALTED_Pos   0U
 
#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)
 
#define SCB_NSACR_CP11_Pos   11U
 
#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)
 
#define SCB_NSACR_CP10_Pos   10U
 
#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)
 
#define SCB_NSACR_CPn_Pos   0U
 
#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)
 
#define SCB_CLIDR_LOUU_Pos   27U
 
#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)
 
#define SCB_CLIDR_LOC_Pos   24U
 
#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)
 
#define SCB_CLIDR_IC_Pos   0U
 
#define SCB_CLIDR_IC_Msk   (1UL << SCB_CLIDR_IC_Pos)
 
#define SCB_CLIDR_DC_Pos   1U
 
#define SCB_CLIDR_DC_Msk   (1UL << SCB_CLIDR_DC_Pos)
 
#define SCB_CTR_FORMAT_Pos   29U
 
#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)
 
#define SCB_CTR_CWG_Pos   24U
 
#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)
 
#define SCB_CTR_ERG_Pos   20U
 
#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)
 
#define SCB_CTR_DMINLINE_Pos   16U
 
#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)
 
#define SCB_CTR_IMINLINE_Pos   0U
 
#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
 
#define SCB_CCSIDR_WT_Pos   31U
 
#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)
 
#define SCB_CCSIDR_WB_Pos   30U
 
#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)
 
#define SCB_CCSIDR_RA_Pos   29U
 
#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)
 
#define SCB_CCSIDR_WA_Pos   28U
 
#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)
 
#define SCB_CCSIDR_NUMSETS_Pos   13U
 
#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
 
#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U
 
#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
 
#define SCB_CCSIDR_LINESIZE_Pos   0U
 
#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
 
#define SCB_CSSELR_LEVEL_Pos   1U
 
#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)
 
#define SCB_CSSELR_IND_Pos   0U
 
#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)
 
#define SCB_STIR_INTID_Pos   0U
 
#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
 
#define SCB_DCISW_LEVEL_Pos   1U
 
#define SCB_DCISW_LEVEL_Msk   (7UL << SCB_DCISW_LEVEL_Pos)
 
#define SCB_DCISW_WAY_Pos   30U
 
#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)
 
#define SCB_DCISW_SET_Pos   5U
 
#define SCB_DCISW_SET_Msk   (0xFFUL << SCB_DCISW_SET_Pos)
 
#define SCB_DCCSW_LEVEL_Pos   1U
 
#define SCB_DCCSW_LEVEL_Msk   (7UL << SCB_DCCSW_LEVEL_Pos)
 
#define SCB_DCCSW_WAY_Pos   30U
 
#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)
 
#define SCB_DCCSW_SET_Pos   5U
 
#define SCB_DCCSW_SET_Msk   (0xFFUL << SCB_DCCSW_SET_Pos)
 
#define SCB_DCCISW_LEVEL_Pos   1U
 
#define SCB_DCCISW_LEVEL_Msk   (7UL << SCB_DCCISW_LEVEL_Pos)
 
#define SCB_DCCISW_WAY_Pos   30U
 
#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)
 
#define SCB_DCCISW_SET_Pos   5U
 
#define SCB_DCCISW_SET_Msk   (0xFFUL << SCB_DCCISW_SET_Pos)
 
#define SCB_ITCMCR_SZ_Pos   3U
 
#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)
 
#define SCB_ITCMCR_EN_Pos   0U
 
#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)
 
#define SCB_DTCMCR_SZ_Pos   3U
 
#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)
 
#define SCB_DTCMCR_EN_Pos   0U
 
#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)
 
#define SCB_CACR_DCCLEAN_Pos   16U
 
#define SCB_CACR_DCCLEAN_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_ICACTIVE_Pos   13U
 
#define SCB_CACR_ICACTIVE_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_DCACTIVE_Pos   12U
 
#define SCB_CACR_DCACTIVE_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_CACR_FORCEWT_Pos   2U
 
#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)
 
#define SCB_AIRCR_IESB_Pos   5U
 
#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)
 
#define SCB_AIRCR_DIT_Pos   4U
 
#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)
 
#define SCB_CCR_TRD_Pos   20U
 
#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)
 
#define SCB_CCR_LOB_Pos   19U
 
#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)
 
#define SCB_DFSR_PMU_Pos   5U
 
#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)
 
#define SCB_NSACR_CP7_Pos   7U
 
#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)
 
#define SCB_NSACR_CP6_Pos   6U
 
#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)
 
#define SCB_NSACR_CP5_Pos   5U
 
#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)
 
#define SCB_NSACR_CP4_Pos   4U
 
#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)
 
#define SCB_NSACR_CP3_Pos   3U
 
#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)
 
#define SCB_NSACR_CP2_Pos   2U
 
#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)
 
#define SCB_NSACR_CP1_Pos   1U
 
#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)
 
#define SCB_NSACR_CP0_Pos   0U
 
#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)
 
#define SCB_ID_DFR_UDE_Pos   28U
 
#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)
 
#define SCB_ID_DFR_MProfDbg_Pos   20U
 
#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)
 
#define SCB_RFSR_V_Pos   31U
 
#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)
 
#define SCB_RFSR_IS_Pos   16U
 
#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)
 
#define SCB_RFSR_UET_Pos   0U
 
#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)
 
#define SCB_AIRCR_IESB_Pos   5U
 
#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)
 
#define SCB_AIRCR_DIT_Pos   4U
 
#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)
 
#define SCB_CCR_TRD_Pos   20U
 
#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)
 
#define SCB_CCR_LOB_Pos   19U
 
#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)
 
#define SCB_DFSR_PMU_Pos   5U
 
#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)
 
#define SCB_NSACR_CP7_Pos   7U
 
#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)
 
#define SCB_NSACR_CP6_Pos   6U
 
#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)
 
#define SCB_NSACR_CP5_Pos   5U
 
#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)
 
#define SCB_NSACR_CP4_Pos   4U
 
#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)
 
#define SCB_NSACR_CP3_Pos   3U
 
#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)
 
#define SCB_NSACR_CP2_Pos   2U
 
#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)
 
#define SCB_NSACR_CP1_Pos   1U
 
#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)
 
#define SCB_NSACR_CP0_Pos   0U
 
#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)
 
#define SCB_ID_DFR_UDE_Pos   28U
 
#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)
 
#define SCB_ID_DFR_MProfDbg_Pos   20U
 
#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)
 
#define SCB_RFSR_V_Pos   31U
 
#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)
 
#define SCB_RFSR_IS_Pos   16U
 
#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)
 
#define SCB_RFSR_UET_Pos   0U
 
#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)
 
#define SCB_AIRCR_IESB_Pos   5U
 
#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)
 
#define SCB_AIRCR_DIT_Pos   4U
 
#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)
 
#define SCB_CCR_TRD_Pos   20U
 
#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)
 
#define SCB_CCR_LOB_Pos   19U
 
#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)
 
#define SCB_DFSR_PMU_Pos   5U
 
#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)
 
#define SCB_NSACR_CP7_Pos   7U
 
#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)
 
#define SCB_NSACR_CP6_Pos   6U
 
#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)
 
#define SCB_NSACR_CP5_Pos   5U
 
#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)
 
#define SCB_NSACR_CP4_Pos   4U
 
#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)
 
#define SCB_NSACR_CP3_Pos   3U
 
#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)
 
#define SCB_NSACR_CP2_Pos   2U
 
#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)
 
#define SCB_NSACR_CP1_Pos   1U
 
#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)
 
#define SCB_NSACR_CP0_Pos   0U
 
#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)
 
#define SCB_ID_DFR_UDE_Pos   28U
 
#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)
 
#define SCB_ID_DFR_MProfDbg_Pos   20U
 
#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)
 
#define SCB_RFSR_V_Pos   31U
 
#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)
 
#define SCB_RFSR_IS_Pos   16U
 
#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)
 
#define SCB_RFSR_UET_Pos   0U
 
#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)
 
#define TPI_ACPR_SWOSCALER_Pos   0U
 
#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
 
#define TPI_FFCR_EnFmt_Pos   0U
 
#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
 
#define TPI_PSCR_PSCount_Pos   0U
 
#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
 
#define TPI_LSR_nTT_Pos   1U
 
#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
 
#define TPI_LSR_SLK_Pos   1U
 
#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
 
#define TPI_LSR_SLI_Pos   0U
 
#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
 
#define MPU_RLAR_PXN_Pos   4U
 
#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DHCSR_S_FPD_Pos   23U
 
#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
 
#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
 
#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
 
#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
 
#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
 
#define CoreDebug_DHCSR_S_SDE_Pos   20U
 
#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
 
#define CoreDebug_DHCSR_C_PMOV_Pos   6U
 
#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
 
#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
 
#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
 
#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_S_FPD_Pos   23U
 
#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)
 
#define DCB_DHCSR_S_SUIDE_Pos   22U
 
#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
 
#define DCB_DHCSR_S_NSUIDE_Pos   21U
 
#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
 
#define DCB_DHCSR_C_PMOV_Pos   6U
 
#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)
 
#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
 
#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
 
#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
 
#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
 
#define DCB_DAUTHCTRL_UIDEN_Pos   10U
 
#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
 
#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
 
#define DCB_DAUTHCTRL_FSDMA_Pos   8U
 
#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
 
#define DIB_DAUTHSTATUS_SUNID_Pos   22U
 
#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )
 
#define DIB_DAUTHSTATUS_SUID_Pos   20U
 
#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )
 
#define DIB_DAUTHSTATUS_NSUNID_Pos   18U
 
#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )
 
#define DIB_DAUTHSTATUS_NSUID_Pos   16U
 
#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )
 
#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U
 
#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)
 
#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U
 
#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_Pos   14U
 
#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)
 
#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U
 
#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)
 
#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U
 
#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)
 
#define ICB_ACTLR_DISNWAMODE_Pos   11U
 
#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)
 
#define ICB_ACTLR_FPEXCODIS_Pos   10U
 
#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)
 
#define ICB_ICTR_INTLINESNUM_Pos   0U
 
#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)
 
#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U
 
#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)
 
#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U
 
#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)
 
#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U
 
#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U
 
#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U
 
#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)
 
#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U
 
#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)
 
#define MEMSYSCTL_MSCR_ECCEN_Pos   1U
 
#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)
 
#define MEMSYSCTL_PFCR_ENABLE_Pos   0U
 
#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)
 
#define MEMSYSCTL_ITCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)
 
#define MEMSYSCTL_ITCMCR_EN_Pos   0U
 
#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)
 
#define MEMSYSCTL_DTCMCR_SZ_Pos   3U
 
#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)
 
#define MEMSYSCTL_DTCMCR_EN_Pos   0U
 
#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)
 
#define MEMSYSCTL_PAHBCR_SZ_Pos   1U
 
#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)
 
#define MEMSYSCTL_PAHBCR_EN_Pos   0U
 
#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U
 
#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U
 
#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U
 
#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U
 
#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U
 
#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U
 
#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U
 
#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U
 
#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U
 
#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)
 
#define EWIC_EVENTSPR_EDBGREQ_Pos   2U
 
#define EWIC_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)
 
#define EWIC_EVENTSPR_NMI_Pos   1U
 
#define EWIC_EVENTSPR_NMI_Msk   (0x1UL << EWIC_EVENTSPR_NMI_Pos)
 
#define EWIC_EVENTSPR_EVENT_Pos   0U
 
#define EWIC_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/)
 
#define EWIC_EVENTMASKA_EDBGREQ_Pos   2U
 
#define EWIC_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)
 
#define EWIC_EVENTMASKA_NMI_Pos   1U
 
#define EWIC_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_EVENTMASKA_NMI_Pos)
 
#define EWIC_EVENTMASKA_EVENT_Pos   0U
 
#define EWIC_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/)
 
#define EWIC_EVENTMASK_IRQ_Pos   0U
 
#define EWIC_EVENTMASK_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/)
 
#define ERRBNK_IEBR0_SWDEF_Pos   30U
 
#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)
 
#define ERRBNK_IEBR0_BANK_Pos   16U
 
#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)
 
#define ERRBNK_IEBR0_LOCATION_Pos   2U
 
#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)
 
#define ERRBNK_IEBR0_LOCKED_Pos   1U
 
#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)
 
#define ERRBNK_IEBR0_VALID_Pos   0U
 
#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)
 
#define ERRBNK_IEBR1_SWDEF_Pos   30U
 
#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)
 
#define ERRBNK_IEBR1_BANK_Pos   16U
 
#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)
 
#define ERRBNK_IEBR1_LOCATION_Pos   2U
 
#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)
 
#define ERRBNK_IEBR1_LOCKED_Pos   1U
 
#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)
 
#define ERRBNK_IEBR1_VALID_Pos   0U
 
#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)
 
#define ERRBNK_DEBR0_SWDEF_Pos   30U
 
#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)
 
#define ERRBNK_DEBR0_TYPE_Pos   17U
 
#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)
 
#define ERRBNK_DEBR0_BANK_Pos   16U
 
#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)
 
#define ERRBNK_DEBR0_LOCATION_Pos   2U
 
#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)
 
#define ERRBNK_DEBR0_LOCKED_Pos   1U
 
#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)
 
#define ERRBNK_DEBR0_VALID_Pos   0U
 
#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)
 
#define ERRBNK_DEBR1_SWDEF_Pos   30U
 
#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)
 
#define ERRBNK_DEBR1_TYPE_Pos   17U
 
#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)
 
#define ERRBNK_DEBR1_BANK_Pos   16U
 
#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)
 
#define ERRBNK_DEBR1_LOCATION_Pos   2U
 
#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)
 
#define ERRBNK_DEBR1_LOCKED_Pos   1U
 
#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)
 
#define ERRBNK_DEBR1_VALID_Pos   0U
 
#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)
 
#define ERRBNK_TEBR0_SWDEF_Pos   30U
 
#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)
 
#define ERRBNK_TEBR0_POISON_Pos   28U
 
#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)
 
#define ERRBNK_TEBR0_TYPE_Pos   27U
 
#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)
 
#define ERRBNK_TEBR0_BANK_Pos   24U
 
#define ERRBNK_TEBR0_BANK_Msk   (0x3UL << ERRBNK_TEBR0_BANK_Pos)
 
#define ERRBNK_TEBR0_LOCATION_Pos   2U
 
#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)
 
#define ERRBNK_TEBR0_LOCKED_Pos   1U
 
#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)
 
#define ERRBNK_TEBR0_VALID_Pos   0U
 
#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)
 
#define ERRBNK_TEBR1_SWDEF_Pos   30U
 
#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)
 
#define ERRBNK_TEBR1_POISON_Pos   28U
 
#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)
 
#define ERRBNK_TEBR1_TYPE_Pos   27U
 
#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)
 
#define ERRBNK_TEBR1_BANK_Pos   24U
 
#define ERRBNK_TEBR1_BANK_Msk   (0x3UL << ERRBNK_TEBR1_BANK_Pos)
 
#define ERRBNK_TEBR1_LOCATION_Pos   2U
 
#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)
 
#define ERRBNK_TEBR1_LOCKED_Pos   1U
 
#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)
 
#define ERRBNK_TEBR1_VALID_Pos   0U
 
#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)
 
#define TPI_ACPR_SWOSCALER_Pos   0U
 
#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)
 
#define TPI_FFCR_EnFmt_Pos   0U
 
#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)
 
#define TPI_PSCR_PSCount_Pos   0U
 
#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)
 
#define TPI_LSR_nTT_Pos   1U
 
#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)
 
#define TPI_LSR_SLK_Pos   1U
 
#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)
 
#define TPI_LSR_SLI_Pos   0U
 
#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)
 
#define MPU_RLAR_PXN_Pos   4U
 
#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)
 
#define FPU_FPDSCR_FZ16_Pos   19U
 
#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)
 
#define FPU_FPDSCR_LTPSIZE_Pos   16U
 
#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)
 
#define FPU_MVFR0_FPRound_Pos   28U
 
#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)
 
#define FPU_MVFR0_FPSqrt_Pos   20U
 
#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)
 
#define FPU_MVFR0_FPDivide_Pos   16U
 
#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)
 
#define FPU_MVFR0_FPDP_Pos   8U
 
#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)
 
#define FPU_MVFR0_FPSP_Pos   4U
 
#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)
 
#define FPU_MVFR0_SIMDReg_Pos   0U
 
#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)
 
#define FPU_MVFR1_FMAC_Pos   28U
 
#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)
 
#define FPU_MVFR1_FPHP_Pos   24U
 
#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)
 
#define FPU_MVFR1_FP16_Pos   20U
 
#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)
 
#define FPU_MVFR1_MVE_Pos   8U
 
#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)
 
#define FPU_MVFR1_FPDNaN_Pos   4U
 
#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)
 
#define FPU_MVFR1_FPFtZ_Pos   0U
 
#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)
 
#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
 
#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
 
#define CoreDebug_DHCSR_S_FPD_Pos   23U
 
#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
 
#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
 
#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
 
#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
 
#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
 
#define CoreDebug_DHCSR_S_SDE_Pos   20U
 
#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
 
#define CoreDebug_DHCSR_C_PMOV_Pos   6U
 
#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
 
#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
 
#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
 
#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
 
#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
 
#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
 
#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
 
#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
 
#define CoreDebug_DSCSR_CDS_Pos   16U
 
#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
 
#define CoreDebug_DSCSR_SBRSEL_Pos   1U
 
#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
 
#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
 
#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
 
#define DCB_DHCSR_S_FPD_Pos   23U
 
#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)
 
#define DCB_DHCSR_S_SUIDE_Pos   22U
 
#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)
 
#define DCB_DHCSR_S_NSUIDE_Pos   21U
 
#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)
 
#define DCB_DHCSR_C_PMOV_Pos   6U
 
#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)
 
#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U
 
#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)
 
#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U
 
#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)
 
#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U
 
#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)
 
#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U
 
#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)
 
#define DCB_DAUTHCTRL_UIDEN_Pos   10U
 
#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)
 
#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U
 
#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)
 
#define DCB_DAUTHCTRL_FSDMA_Pos   8U
 
#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)
 
#define DIB_DAUTHSTATUS_SUNID_Pos   22U
 
#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )
 
#define DIB_DAUTHSTATUS_SUID_Pos   20U
 
#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )
 
#define DIB_DAUTHSTATUS_NSUNID_Pos   18U
 
#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )
 
#define DIB_DAUTHSTATUS_NSUID_Pos   16U
 
#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )
 
#define MEMSYSCTL_BASE   (0xE001E000UL)
 
#define ERRBNK_BASE   (0xE001E100UL)
 
#define PWRMODCTL_BASE   (0xE001E300UL)
 
#define EWIC_BASE   (0xE001E400UL)
 
#define PRCCFGINF_BASE   (0xE001E700UL)
 
#define ICB   ((ICB_Type *) SCS_BASE )
 
#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )
 
#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )
 
#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )
 
#define EWIC   ((EWIC_Type *) EWIC_BASE )
 
#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_VTOR_TBLBASE_Pos   29U
 
#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)
 
#define SCB_AIRCR_VECTRESET_Pos   0U
 
#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
 
#define SCB_CCR_STKALIGN_Pos   9U
 
#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)
 
#define SCB_CCR_NONBASETHRDENA_Pos   0U
 
#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   8U
 
#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define SCnSCB_ACTLR_DISMCYCINT_Pos   0U
 
#define SCnSCB_ACTLR_DISMCYCINT_Msk   (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
 
#define MPU_RBAR_ADDR_Pos   8U
 
#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)
 
#define MPU_RBAR_VALID_Pos   4U
 
#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)
 
#define MPU_RBAR_REGION_Pos   0U
 
#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
 
#define MPU_RASR_ATTRS_Pos   16U
 
#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 
#define MPU_RASR_XN_Pos   28U
 
#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)
 
#define MPU_RASR_AP_Pos   24U
 
#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)
 
#define MPU_RASR_TEX_Pos   19U
 
#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)
 
#define MPU_RASR_S_Pos   18U
 
#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)
 
#define MPU_RASR_C_Pos   17U
 
#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)
 
#define MPU_RASR_B_Pos   16U
 
#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)
 
#define MPU_RASR_SRD_Pos   8U
 
#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)
 
#define MPU_RASR_SIZE_Pos   1U
 
#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)
 
#define MPU_RASR_ENABLE_Pos   0U
 
#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)
 
#define SCB_ITCMCR_RETEN_Pos   2U
 
#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)
 
#define SCB_ITCMCR_RMW_Pos   1U
 
#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)
 
#define SCB_DTCMCR_RETEN_Pos   2U
 
#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)
 
#define SCB_DTCMCR_RMW_Pos   1U
 
#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)
 
#define SCB_AHBPCR_SZ_Pos   1U
 
#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)
 
#define SCB_AHBPCR_EN_Pos   0U
 
#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)
 
#define SCB_CACR_ECCEN_Pos   1U
 
#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
 
#define SCB_CACR_ECCDIS_Pos   1U
 
#define SCB_CACR_ECCDIS_Msk   (1UL << SCB_CACR_ECCDIS_Pos)
 
#define SCB_CACR_SIWT_Pos   0U
 
#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)
 
#define SCB_AHBSCR_INITCOUNT_Pos   11U
 
#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos)
 
#define SCB_AHBSCR_TPRI_Pos   2U
 
#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBSCR_TPRI_Pos)
 
#define SCB_AHBSCR_CTL_Pos   0U
 
#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBSCR_CTL_Pos*/)
 
#define SCB_ABFSR_AXIMTYPE_Pos   8U
 
#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)
 
#define SCB_ABFSR_EPPB_Pos   4U
 
#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)
 
#define SCB_ABFSR_AXIM_Pos   3U
 
#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)
 
#define SCB_ABFSR_AHBP_Pos   2U
 
#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)
 
#define SCB_ABFSR_DTCM_Pos   1U
 
#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)
 
#define SCB_ABFSR_ITCM_Pos   0U
 
#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
 

Detailed Description

Type definitions for the System Control Block Registers.

Data Structure Documentation

◆ SCB_Type

struct SCB_Type

Structure type to access the System Control Block (SCB).

Definition at line 511 of file core_armv81mml.h.

◆ EMSS_Type

struct EMSS_Type

Definition at line 560 of file core_starmc1.h.

Macro Definition Documentation

◆ SCB_CPUID_IMPLEMENTER_Pos [1/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 563 of file core_armv81mml.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [1/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 564 of file core_armv81mml.h.

◆ SCB_CPUID_VARIANT_Pos [1/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 566 of file core_armv81mml.h.

◆ SCB_CPUID_VARIANT_Msk [1/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 567 of file core_armv81mml.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [1/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 569 of file core_armv81mml.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [1/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 570 of file core_armv81mml.h.

◆ SCB_CPUID_PARTNO_Pos [1/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 572 of file core_armv81mml.h.

◆ SCB_CPUID_PARTNO_Msk [1/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 573 of file core_armv81mml.h.

◆ SCB_CPUID_REVISION_Pos [1/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 575 of file core_armv81mml.h.

◆ SCB_CPUID_REVISION_Msk [1/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 576 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMISET_Pos [1/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 579 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMISET_Msk [1/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 580 of file core_armv81mml.h.

◆ SCB_ICSR_NMIPENDSET_Pos [1/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

Definition at line 582 of file core_armv81mml.h.

◆ SCB_ICSR_NMIPENDSET_Msk [1/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

Definition at line 583 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMICLR_Pos [1/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 585 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMICLR_Msk [1/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 586 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVSET_Pos [1/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 588 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVSET_Msk [1/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 589 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVCLR_Pos [1/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 591 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVCLR_Msk [1/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 592 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTSET_Pos [1/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 594 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTSET_Msk [1/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 595 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTCLR_Pos [1/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 597 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTCLR_Msk [1/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 598 of file core_armv81mml.h.

◆ SCB_ICSR_STTNS_Pos [1/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 600 of file core_armv81mml.h.

◆ SCB_ICSR_STTNS_Msk [1/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 601 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [1/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 603 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [1/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 604 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPENDING_Pos [1/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 606 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPENDING_Msk [1/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 607 of file core_armv81mml.h.

◆ SCB_ICSR_VECTPENDING_Pos [1/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 609 of file core_armv81mml.h.

◆ SCB_ICSR_VECTPENDING_Msk [1/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 610 of file core_armv81mml.h.

◆ SCB_ICSR_RETTOBASE_Pos [1/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 612 of file core_armv81mml.h.

◆ SCB_ICSR_RETTOBASE_Msk [1/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 613 of file core_armv81mml.h.

◆ SCB_ICSR_VECTACTIVE_Pos [1/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 615 of file core_armv81mml.h.

◆ SCB_ICSR_VECTACTIVE_Msk [1/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 616 of file core_armv81mml.h.

◆ SCB_VTOR_TBLOFF_Pos [1/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 619 of file core_armv81mml.h.

◆ SCB_VTOR_TBLOFF_Msk [1/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 620 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEY_Pos [1/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 623 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEY_Msk [1/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 624 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [1/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 626 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [1/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 627 of file core_armv81mml.h.

◆ SCB_AIRCR_ENDIANESS_Pos [1/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 629 of file core_armv81mml.h.

◆ SCB_AIRCR_ENDIANESS_Msk [1/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 630 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIS_Pos [1/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 632 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIS_Msk [1/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 633 of file core_armv81mml.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [1/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 635 of file core_armv81mml.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [1/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 636 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIGROUP_Pos [1/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 638 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIGROUP_Msk [1/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 639 of file core_armv81mml.h.

◆ SCB_AIRCR_IESB_Pos [1/3]

#define SCB_AIRCR_IESB_Pos   5U

SCB AIRCR: Implicit ESB Enable Position

Definition at line 641 of file core_armv81mml.h.

◆ SCB_AIRCR_IESB_Msk [1/3]

#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)

SCB AIRCR: Implicit ESB Enable Mask

Definition at line 642 of file core_armv81mml.h.

◆ SCB_AIRCR_DIT_Pos [1/3]

#define SCB_AIRCR_DIT_Pos   4U

SCB AIRCR: Data Independent Timing Position

Definition at line 644 of file core_armv81mml.h.

◆ SCB_AIRCR_DIT_Msk [1/3]

#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)

SCB AIRCR: Data Independent Timing Mask

Definition at line 645 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [1/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 647 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [1/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 648 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [1/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 650 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [1/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 651 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [1/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 653 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [1/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 654 of file core_armv81mml.h.

◆ SCB_SCR_SEVONPEND_Pos [1/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 657 of file core_armv81mml.h.

◆ SCB_SCR_SEVONPEND_Msk [1/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 658 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [1/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 660 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [1/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 661 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEP_Pos [1/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 663 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEP_Msk [1/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 664 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [1/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 666 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [1/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 667 of file core_armv81mml.h.

◆ SCB_CCR_TRD_Pos [1/3]

#define SCB_CCR_TRD_Pos   20U

SCB CCR: TRD Position

Definition at line 670 of file core_armv81mml.h.

◆ SCB_CCR_TRD_Msk [1/3]

#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)

SCB CCR: TRD Mask

Definition at line 671 of file core_armv81mml.h.

◆ SCB_CCR_LOB_Pos [1/3]

#define SCB_CCR_LOB_Pos   19U

SCB CCR: LOB Position

Definition at line 673 of file core_armv81mml.h.

◆ SCB_CCR_LOB_Msk [1/3]

#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)

SCB CCR: LOB Mask

Definition at line 674 of file core_armv81mml.h.

◆ SCB_CCR_BP_Pos [1/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

Definition at line 676 of file core_armv81mml.h.

◆ SCB_CCR_BP_Msk [1/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

Definition at line 677 of file core_armv81mml.h.

◆ SCB_CCR_IC_Pos [1/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

Definition at line 679 of file core_armv81mml.h.

◆ SCB_CCR_IC_Msk [1/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

Definition at line 680 of file core_armv81mml.h.

◆ SCB_CCR_DC_Pos [1/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

Definition at line 682 of file core_armv81mml.h.

◆ SCB_CCR_DC_Msk [1/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

Definition at line 683 of file core_armv81mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [1/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 685 of file core_armv81mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [1/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 686 of file core_armv81mml.h.

◆ SCB_CCR_BFHFNMIGN_Pos [1/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 688 of file core_armv81mml.h.

◆ SCB_CCR_BFHFNMIGN_Msk [1/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 689 of file core_armv81mml.h.

◆ SCB_CCR_DIV_0_TRP_Pos [1/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 691 of file core_armv81mml.h.

◆ SCB_CCR_DIV_0_TRP_Msk [1/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 692 of file core_armv81mml.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [1/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 694 of file core_armv81mml.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [1/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 695 of file core_armv81mml.h.

◆ SCB_CCR_USERSETMPEND_Pos [1/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 697 of file core_armv81mml.h.

◆ SCB_CCR_USERSETMPEND_Msk [1/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 698 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [1/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 701 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [1/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 702 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [1/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 704 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [1/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 705 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [1/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 707 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [1/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 708 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [1/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 710 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [1/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 711 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [1/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 713 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [1/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 714 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [1/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 716 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [1/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 717 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [1/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 719 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [1/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 720 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [1/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 722 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [1/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 723 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [1/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 725 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [1/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 726 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [1/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 728 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [1/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 729 of file core_armv81mml.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [1/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 731 of file core_armv81mml.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [1/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 732 of file core_armv81mml.h.

◆ SCB_SHCSR_PENDSVACT_Pos [1/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 734 of file core_armv81mml.h.

◆ SCB_SHCSR_PENDSVACT_Msk [1/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 735 of file core_armv81mml.h.

◆ SCB_SHCSR_MONITORACT_Pos [1/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 737 of file core_armv81mml.h.

◆ SCB_SHCSR_MONITORACT_Msk [1/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 738 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLACT_Pos [1/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 740 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLACT_Msk [1/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 741 of file core_armv81mml.h.

◆ SCB_SHCSR_NMIACT_Pos [1/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 743 of file core_armv81mml.h.

◆ SCB_SHCSR_NMIACT_Msk [1/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 744 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [1/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 746 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [1/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 747 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [1/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 749 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [1/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 750 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [1/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 752 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [1/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 753 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [1/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 755 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [1/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 756 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [1/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 758 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [1/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 759 of file core_armv81mml.h.

◆ SCB_CFSR_USGFAULTSR_Pos [1/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 762 of file core_armv81mml.h.

◆ SCB_CFSR_USGFAULTSR_Msk [1/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 763 of file core_armv81mml.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [1/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 765 of file core_armv81mml.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [1/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 766 of file core_armv81mml.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [1/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 768 of file core_armv81mml.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [1/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 769 of file core_armv81mml.h.

◆ SCB_CFSR_MMARVALID_Pos [1/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 772 of file core_armv81mml.h.

◆ SCB_CFSR_MMARVALID_Msk [1/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 773 of file core_armv81mml.h.

◆ SCB_CFSR_MLSPERR_Pos [1/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 775 of file core_armv81mml.h.

◆ SCB_CFSR_MLSPERR_Msk [1/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 776 of file core_armv81mml.h.

◆ SCB_CFSR_MSTKERR_Pos [1/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 778 of file core_armv81mml.h.

◆ SCB_CFSR_MSTKERR_Msk [1/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 779 of file core_armv81mml.h.

◆ SCB_CFSR_MUNSTKERR_Pos [1/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 781 of file core_armv81mml.h.

◆ SCB_CFSR_MUNSTKERR_Msk [1/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 782 of file core_armv81mml.h.

◆ SCB_CFSR_DACCVIOL_Pos [1/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 784 of file core_armv81mml.h.

◆ SCB_CFSR_DACCVIOL_Msk [1/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 785 of file core_armv81mml.h.

◆ SCB_CFSR_IACCVIOL_Pos [1/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 787 of file core_armv81mml.h.

◆ SCB_CFSR_IACCVIOL_Msk [1/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 788 of file core_armv81mml.h.

◆ SCB_CFSR_BFARVALID_Pos [1/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 791 of file core_armv81mml.h.

◆ SCB_CFSR_BFARVALID_Msk [1/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 792 of file core_armv81mml.h.

◆ SCB_CFSR_LSPERR_Pos [1/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 794 of file core_armv81mml.h.

◆ SCB_CFSR_LSPERR_Msk [1/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 795 of file core_armv81mml.h.

◆ SCB_CFSR_STKERR_Pos [1/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 797 of file core_armv81mml.h.

◆ SCB_CFSR_STKERR_Msk [1/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 798 of file core_armv81mml.h.

◆ SCB_CFSR_UNSTKERR_Pos [1/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 800 of file core_armv81mml.h.

◆ SCB_CFSR_UNSTKERR_Msk [1/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 801 of file core_armv81mml.h.

◆ SCB_CFSR_IMPRECISERR_Pos [1/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 803 of file core_armv81mml.h.

◆ SCB_CFSR_IMPRECISERR_Msk [1/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 804 of file core_armv81mml.h.

◆ SCB_CFSR_PRECISERR_Pos [1/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 806 of file core_armv81mml.h.

◆ SCB_CFSR_PRECISERR_Msk [1/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 807 of file core_armv81mml.h.

◆ SCB_CFSR_IBUSERR_Pos [1/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 809 of file core_armv81mml.h.

◆ SCB_CFSR_IBUSERR_Msk [1/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 810 of file core_armv81mml.h.

◆ SCB_CFSR_DIVBYZERO_Pos [1/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 813 of file core_armv81mml.h.

◆ SCB_CFSR_DIVBYZERO_Msk [1/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 814 of file core_armv81mml.h.

◆ SCB_CFSR_UNALIGNED_Pos [1/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 816 of file core_armv81mml.h.

◆ SCB_CFSR_UNALIGNED_Msk [1/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 817 of file core_armv81mml.h.

◆ SCB_CFSR_STKOF_Pos [1/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 819 of file core_armv81mml.h.

◆ SCB_CFSR_STKOF_Msk [1/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 820 of file core_armv81mml.h.

◆ SCB_CFSR_NOCP_Pos [1/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 822 of file core_armv81mml.h.

◆ SCB_CFSR_NOCP_Msk [1/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 823 of file core_armv81mml.h.

◆ SCB_CFSR_INVPC_Pos [1/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 825 of file core_armv81mml.h.

◆ SCB_CFSR_INVPC_Msk [1/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 826 of file core_armv81mml.h.

◆ SCB_CFSR_INVSTATE_Pos [1/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 828 of file core_armv81mml.h.

◆ SCB_CFSR_INVSTATE_Msk [1/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 829 of file core_armv81mml.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [1/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 831 of file core_armv81mml.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [1/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 832 of file core_armv81mml.h.

◆ SCB_HFSR_DEBUGEVT_Pos [1/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 835 of file core_armv81mml.h.

◆ SCB_HFSR_DEBUGEVT_Msk [1/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 836 of file core_armv81mml.h.

◆ SCB_HFSR_FORCED_Pos [1/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 838 of file core_armv81mml.h.

◆ SCB_HFSR_FORCED_Msk [1/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 839 of file core_armv81mml.h.

◆ SCB_HFSR_VECTTBL_Pos [1/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 841 of file core_armv81mml.h.

◆ SCB_HFSR_VECTTBL_Msk [1/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 842 of file core_armv81mml.h.

◆ SCB_DFSR_PMU_Pos [1/3]

#define SCB_DFSR_PMU_Pos   5U

SCB DFSR: PMU Position

Definition at line 845 of file core_armv81mml.h.

◆ SCB_DFSR_PMU_Msk [1/3]

#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)

SCB DFSR: PMU Mask

Definition at line 846 of file core_armv81mml.h.

◆ SCB_DFSR_EXTERNAL_Pos [1/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 848 of file core_armv81mml.h.

◆ SCB_DFSR_EXTERNAL_Msk [1/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 849 of file core_armv81mml.h.

◆ SCB_DFSR_VCATCH_Pos [1/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 851 of file core_armv81mml.h.

◆ SCB_DFSR_VCATCH_Msk [1/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 852 of file core_armv81mml.h.

◆ SCB_DFSR_DWTTRAP_Pos [1/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 854 of file core_armv81mml.h.

◆ SCB_DFSR_DWTTRAP_Msk [1/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 855 of file core_armv81mml.h.

◆ SCB_DFSR_BKPT_Pos [1/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 857 of file core_armv81mml.h.

◆ SCB_DFSR_BKPT_Msk [1/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 858 of file core_armv81mml.h.

◆ SCB_DFSR_HALTED_Pos [1/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 860 of file core_armv81mml.h.

◆ SCB_DFSR_HALTED_Msk [1/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 861 of file core_armv81mml.h.

◆ SCB_NSACR_CP11_Pos [1/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 864 of file core_armv81mml.h.

◆ SCB_NSACR_CP11_Msk [1/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 865 of file core_armv81mml.h.

◆ SCB_NSACR_CP10_Pos [1/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 867 of file core_armv81mml.h.

◆ SCB_NSACR_CP10_Msk [1/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 868 of file core_armv81mml.h.

◆ SCB_NSACR_CP7_Pos [1/3]

#define SCB_NSACR_CP7_Pos   7U

SCB NSACR: CP7 Position

Definition at line 870 of file core_armv81mml.h.

◆ SCB_NSACR_CP7_Msk [1/3]

#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)

SCB NSACR: CP7 Mask

Definition at line 871 of file core_armv81mml.h.

◆ SCB_NSACR_CP6_Pos [1/3]

#define SCB_NSACR_CP6_Pos   6U

SCB NSACR: CP6 Position

Definition at line 873 of file core_armv81mml.h.

◆ SCB_NSACR_CP6_Msk [1/3]

#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)

SCB NSACR: CP6 Mask

Definition at line 874 of file core_armv81mml.h.

◆ SCB_NSACR_CP5_Pos [1/3]

#define SCB_NSACR_CP5_Pos   5U

SCB NSACR: CP5 Position

Definition at line 876 of file core_armv81mml.h.

◆ SCB_NSACR_CP5_Msk [1/3]

#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)

SCB NSACR: CP5 Mask

Definition at line 877 of file core_armv81mml.h.

◆ SCB_NSACR_CP4_Pos [1/3]

#define SCB_NSACR_CP4_Pos   4U

SCB NSACR: CP4 Position

Definition at line 879 of file core_armv81mml.h.

◆ SCB_NSACR_CP4_Msk [1/3]

#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)

SCB NSACR: CP4 Mask

Definition at line 880 of file core_armv81mml.h.

◆ SCB_NSACR_CP3_Pos [1/3]

#define SCB_NSACR_CP3_Pos   3U

SCB NSACR: CP3 Position

Definition at line 882 of file core_armv81mml.h.

◆ SCB_NSACR_CP3_Msk [1/3]

#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)

SCB NSACR: CP3 Mask

Definition at line 883 of file core_armv81mml.h.

◆ SCB_NSACR_CP2_Pos [1/3]

#define SCB_NSACR_CP2_Pos   2U

SCB NSACR: CP2 Position

Definition at line 885 of file core_armv81mml.h.

◆ SCB_NSACR_CP2_Msk [1/3]

#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)

SCB NSACR: CP2 Mask

Definition at line 886 of file core_armv81mml.h.

◆ SCB_NSACR_CP1_Pos [1/3]

#define SCB_NSACR_CP1_Pos   1U

SCB NSACR: CP1 Position

Definition at line 888 of file core_armv81mml.h.

◆ SCB_NSACR_CP1_Msk [1/3]

#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)

SCB NSACR: CP1 Mask

Definition at line 889 of file core_armv81mml.h.

◆ SCB_NSACR_CP0_Pos [1/3]

#define SCB_NSACR_CP0_Pos   0U

SCB NSACR: CP0 Position

Definition at line 891 of file core_armv81mml.h.

◆ SCB_NSACR_CP0_Msk [1/3]

#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)

SCB NSACR: CP0 Mask

Definition at line 892 of file core_armv81mml.h.

◆ SCB_ID_DFR_UDE_Pos [1/3]

#define SCB_ID_DFR_UDE_Pos   28U

SCB ID_DFR: UDE Position

Definition at line 895 of file core_armv81mml.h.

◆ SCB_ID_DFR_UDE_Msk [1/3]

#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)

SCB ID_DFR: UDE Mask

Definition at line 896 of file core_armv81mml.h.

◆ SCB_ID_DFR_MProfDbg_Pos [1/3]

#define SCB_ID_DFR_MProfDbg_Pos   20U

SCB ID_DFR: MProfDbg Position

Definition at line 898 of file core_armv81mml.h.

◆ SCB_ID_DFR_MProfDbg_Msk [1/3]

#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)

SCB ID_DFR: MProfDbg Mask

Definition at line 899 of file core_armv81mml.h.

◆ SCB_CLIDR_LOUU_Pos [1/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 902 of file core_armv81mml.h.

◆ SCB_CLIDR_LOUU_Msk [1/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 903 of file core_armv81mml.h.

◆ SCB_CLIDR_LOC_Pos [1/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 905 of file core_armv81mml.h.

◆ SCB_CLIDR_LOC_Msk [1/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 906 of file core_armv81mml.h.

◆ SCB_CTR_FORMAT_Pos [1/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 909 of file core_armv81mml.h.

◆ SCB_CTR_FORMAT_Msk [1/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 910 of file core_armv81mml.h.

◆ SCB_CTR_CWG_Pos [1/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 912 of file core_armv81mml.h.

◆ SCB_CTR_CWG_Msk [1/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 913 of file core_armv81mml.h.

◆ SCB_CTR_ERG_Pos [1/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 915 of file core_armv81mml.h.

◆ SCB_CTR_ERG_Msk [1/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 916 of file core_armv81mml.h.

◆ SCB_CTR_DMINLINE_Pos [1/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 918 of file core_armv81mml.h.

◆ SCB_CTR_DMINLINE_Msk [1/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 919 of file core_armv81mml.h.

◆ SCB_CTR_IMINLINE_Pos [1/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 921 of file core_armv81mml.h.

◆ SCB_CTR_IMINLINE_Msk [1/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 922 of file core_armv81mml.h.

◆ SCB_CCSIDR_WT_Pos [1/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 925 of file core_armv81mml.h.

◆ SCB_CCSIDR_WT_Msk [1/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 926 of file core_armv81mml.h.

◆ SCB_CCSIDR_WB_Pos [1/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 928 of file core_armv81mml.h.

◆ SCB_CCSIDR_WB_Msk [1/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 929 of file core_armv81mml.h.

◆ SCB_CCSIDR_RA_Pos [1/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 931 of file core_armv81mml.h.

◆ SCB_CCSIDR_RA_Msk [1/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 932 of file core_armv81mml.h.

◆ SCB_CCSIDR_WA_Pos [1/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 934 of file core_armv81mml.h.

◆ SCB_CCSIDR_WA_Msk [1/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 935 of file core_armv81mml.h.

◆ SCB_CCSIDR_NUMSETS_Pos [1/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 937 of file core_armv81mml.h.

◆ SCB_CCSIDR_NUMSETS_Msk [1/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 938 of file core_armv81mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [1/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 940 of file core_armv81mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [1/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 941 of file core_armv81mml.h.

◆ SCB_CCSIDR_LINESIZE_Pos [1/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 943 of file core_armv81mml.h.

◆ SCB_CCSIDR_LINESIZE_Msk [1/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 944 of file core_armv81mml.h.

◆ SCB_CSSELR_LEVEL_Pos [1/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 947 of file core_armv81mml.h.

◆ SCB_CSSELR_LEVEL_Msk [1/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 948 of file core_armv81mml.h.

◆ SCB_CSSELR_IND_Pos [1/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 950 of file core_armv81mml.h.

◆ SCB_CSSELR_IND_Msk [1/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 951 of file core_armv81mml.h.

◆ SCB_STIR_INTID_Pos [1/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 954 of file core_armv81mml.h.

◆ SCB_STIR_INTID_Msk [1/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 955 of file core_armv81mml.h.

◆ SCB_RFSR_V_Pos [1/3]

#define SCB_RFSR_V_Pos   31U

SCB RFSR: V Position

Definition at line 958 of file core_armv81mml.h.

◆ SCB_RFSR_V_Msk [1/3]

#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)

SCB RFSR: V Mask

Definition at line 959 of file core_armv81mml.h.

◆ SCB_RFSR_IS_Pos [1/3]

#define SCB_RFSR_IS_Pos   16U

SCB RFSR: IS Position

Definition at line 961 of file core_armv81mml.h.

◆ SCB_RFSR_IS_Msk [1/3]

#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)

SCB RFSR: IS Mask

Definition at line 962 of file core_armv81mml.h.

◆ SCB_RFSR_UET_Pos [1/3]

#define SCB_RFSR_UET_Pos   0U

SCB RFSR: UET Position

Definition at line 964 of file core_armv81mml.h.

◆ SCB_RFSR_UET_Msk [1/3]

#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)

SCB RFSR: UET Mask

Definition at line 965 of file core_armv81mml.h.

◆ SCB_DCISW_WAY_Pos [1/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 968 of file core_armv81mml.h.

◆ SCB_DCISW_WAY_Msk [1/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 969 of file core_armv81mml.h.

◆ SCB_DCISW_SET_Pos [1/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 971 of file core_armv81mml.h.

◆ SCB_DCISW_SET_Msk [1/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 972 of file core_armv81mml.h.

◆ SCB_DCCSW_WAY_Pos [1/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 975 of file core_armv81mml.h.

◆ SCB_DCCSW_WAY_Msk [1/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 976 of file core_armv81mml.h.

◆ SCB_DCCSW_SET_Pos [1/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 978 of file core_armv81mml.h.

◆ SCB_DCCSW_SET_Msk [1/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 979 of file core_armv81mml.h.

◆ SCB_DCCISW_WAY_Pos [1/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 982 of file core_armv81mml.h.

◆ SCB_DCCISW_WAY_Msk [1/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 983 of file core_armv81mml.h.

◆ SCB_DCCISW_SET_Pos [1/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 985 of file core_armv81mml.h.

◆ SCB_DCCISW_SET_Msk [1/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 986 of file core_armv81mml.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [2/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 401 of file core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [2/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 402 of file core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Pos [2/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 404 of file core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Msk [2/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 405 of file core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [2/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 407 of file core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [2/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 408 of file core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Pos [2/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 410 of file core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Msk [2/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 411 of file core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Pos [2/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 413 of file core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Msk [2/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 414 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Pos [2/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 417 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Msk [2/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 418 of file core_armv8mbl.h.

◆ SCB_ICSR_NMIPENDSET_Pos [2/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

Definition at line 420 of file core_armv8mbl.h.

◆ SCB_ICSR_NMIPENDSET_Msk [2/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

Definition at line 421 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Pos [2/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 423 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Msk [2/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 424 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Pos [2/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 426 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Msk [2/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 427 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Pos [2/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 429 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Msk [2/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 430 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Pos [2/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 432 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Msk [2/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 433 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Pos [2/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 435 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Msk [2/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 436 of file core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Pos [2/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 438 of file core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Msk [2/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 439 of file core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [2/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 441 of file core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [2/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 442 of file core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Pos [2/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 444 of file core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Msk [2/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 445 of file core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Pos [2/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 447 of file core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Msk [2/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 448 of file core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Pos [2/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 450 of file core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Msk [2/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 451 of file core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Pos [2/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 453 of file core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Msk [2/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 454 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Pos [2/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 463 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Msk [2/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 464 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [2/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 466 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [2/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 467 of file core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Pos [2/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 469 of file core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Msk [2/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 470 of file core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Pos [2/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 472 of file core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Msk [2/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 473 of file core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [2/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 475 of file core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [2/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 476 of file core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [2/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 478 of file core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [2/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 479 of file core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [2/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 481 of file core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [2/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 482 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [2/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 484 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [2/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 485 of file core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Pos [2/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 488 of file core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Msk [2/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 489 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [2/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 491 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [2/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 492 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Pos [2/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 494 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Msk [2/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 495 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [2/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 497 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [2/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 498 of file core_armv8mbl.h.

◆ SCB_CCR_BP_Pos [2/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

Definition at line 501 of file core_armv8mbl.h.

◆ SCB_CCR_BP_Msk [2/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

Definition at line 502 of file core_armv8mbl.h.

◆ SCB_CCR_IC_Pos [2/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

Definition at line 504 of file core_armv8mbl.h.

◆ SCB_CCR_IC_Msk [2/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

Definition at line 505 of file core_armv8mbl.h.

◆ SCB_CCR_DC_Pos [2/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

Definition at line 507 of file core_armv8mbl.h.

◆ SCB_CCR_DC_Msk [2/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

Definition at line 508 of file core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [2/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 510 of file core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [2/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 511 of file core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Pos [2/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 513 of file core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Msk [2/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 514 of file core_armv8mbl.h.

◆ SCB_CCR_DIV_0_TRP_Pos [2/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 516 of file core_armv8mbl.h.

◆ SCB_CCR_DIV_0_TRP_Msk [2/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 517 of file core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [2/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 519 of file core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [2/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 520 of file core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Pos [2/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 522 of file core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Msk [2/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 523 of file core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [2/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 526 of file core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [2/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 527 of file core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [2/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 529 of file core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [2/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 530 of file core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [2/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 532 of file core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [2/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 533 of file core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Pos [2/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 535 of file core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Msk [2/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 536 of file core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Pos [2/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 538 of file core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Msk [2/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 539 of file core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Pos [2/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 541 of file core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Msk [2/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 542 of file core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [2/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 544 of file core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [2/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 545 of file core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [3/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 555 of file core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [3/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 556 of file core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Pos [3/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 558 of file core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Msk [3/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 559 of file core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [3/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 561 of file core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [3/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 562 of file core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Pos [3/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 564 of file core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Msk [3/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 565 of file core_armv8mml.h.

◆ SCB_CPUID_REVISION_Pos [3/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 567 of file core_armv8mml.h.

◆ SCB_CPUID_REVISION_Msk [3/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 568 of file core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Pos [3/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 571 of file core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Msk [3/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 572 of file core_armv8mml.h.

◆ SCB_ICSR_NMIPENDSET_Pos [3/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

Definition at line 574 of file core_armv8mml.h.

◆ SCB_ICSR_NMIPENDSET_Msk [3/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

Definition at line 575 of file core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Pos [3/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 577 of file core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Msk [3/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 578 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Pos [3/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 580 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Msk [3/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 581 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Pos [3/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 583 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Msk [3/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 584 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Pos [3/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 586 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Msk [3/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 587 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Pos [3/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 589 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Msk [3/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 590 of file core_armv8mml.h.

◆ SCB_ICSR_STTNS_Pos [3/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 592 of file core_armv8mml.h.

◆ SCB_ICSR_STTNS_Msk [3/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 593 of file core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [3/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 595 of file core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [3/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 596 of file core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Pos [3/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 598 of file core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Msk [3/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 599 of file core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Pos [3/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 601 of file core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Msk [3/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 602 of file core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Pos [3/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 604 of file core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Msk [3/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 605 of file core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Pos [3/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 607 of file core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Msk [3/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 608 of file core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Pos [2/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 611 of file core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Msk [2/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 612 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Pos [3/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 615 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Msk [3/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 616 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [3/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 618 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [3/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 619 of file core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Pos [3/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 621 of file core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Msk [3/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 622 of file core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Pos [3/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 624 of file core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Msk [3/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 625 of file core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [3/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 627 of file core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [3/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 628 of file core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Pos [2/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 630 of file core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Msk [2/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 631 of file core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [3/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 633 of file core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [3/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 634 of file core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [3/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 636 of file core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [3/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 637 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [3/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 639 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [3/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 640 of file core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Pos [3/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 643 of file core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Msk [3/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 644 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [3/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 646 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [3/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 647 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Pos [3/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 649 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Msk [3/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 650 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [3/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 652 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [3/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 653 of file core_armv8mml.h.

◆ SCB_CCR_BP_Pos [3/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

Definition at line 656 of file core_armv8mml.h.

◆ SCB_CCR_BP_Msk [3/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

Definition at line 657 of file core_armv8mml.h.

◆ SCB_CCR_IC_Pos [3/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

Definition at line 659 of file core_armv8mml.h.

◆ SCB_CCR_IC_Msk [3/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

Definition at line 660 of file core_armv8mml.h.

◆ SCB_CCR_DC_Pos [3/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

Definition at line 662 of file core_armv8mml.h.

◆ SCB_CCR_DC_Msk [3/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

Definition at line 663 of file core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [3/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 665 of file core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [3/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 666 of file core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Pos [3/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 668 of file core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Msk [3/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 669 of file core_armv8mml.h.

◆ SCB_CCR_DIV_0_TRP_Pos [3/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 671 of file core_armv8mml.h.

◆ SCB_CCR_DIV_0_TRP_Msk [3/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 672 of file core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [3/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 674 of file core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [3/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 675 of file core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Pos [3/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 677 of file core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Msk [3/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 678 of file core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [3/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 681 of file core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [3/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 682 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [2/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 684 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [2/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 685 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [2/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 687 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [2/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 688 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [2/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 690 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [2/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 691 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [2/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 693 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [2/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 694 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [2/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 696 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [2/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 697 of file core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [3/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 699 of file core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [3/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 700 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [2/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 702 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [2/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 703 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [2/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 705 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [2/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 706 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [2/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 708 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [2/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 709 of file core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [3/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 711 of file core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [3/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 712 of file core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Pos [3/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 714 of file core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Msk [3/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 715 of file core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Pos [2/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 717 of file core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Msk [2/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 718 of file core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Pos [3/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 720 of file core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Msk [3/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 721 of file core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Pos [3/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 723 of file core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Msk [3/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 724 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [2/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 726 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [2/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 727 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [2/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 729 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [2/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 730 of file core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [3/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 732 of file core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [3/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 733 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [2/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 735 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [2/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 736 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [2/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 738 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [2/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 739 of file core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Pos [2/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 742 of file core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Msk [2/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 743 of file core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [2/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 745 of file core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [2/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 746 of file core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [2/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 748 of file core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [2/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 749 of file core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Pos [2/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 752 of file core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Msk [2/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 753 of file core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Pos [2/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 755 of file core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Msk [2/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 756 of file core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Pos [2/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 758 of file core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Msk [2/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 759 of file core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Pos [2/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 761 of file core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Msk [2/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 762 of file core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Pos [2/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 764 of file core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Msk [2/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 765 of file core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Pos [2/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 767 of file core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Msk [2/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 768 of file core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Pos [2/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 771 of file core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Msk [2/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 772 of file core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Pos [2/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 774 of file core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Msk [2/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 775 of file core_armv8mml.h.

◆ SCB_CFSR_STKERR_Pos [2/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 777 of file core_armv8mml.h.

◆ SCB_CFSR_STKERR_Msk [2/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 778 of file core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Pos [2/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 780 of file core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Msk [2/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 781 of file core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Pos [2/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 783 of file core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Msk [2/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 784 of file core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Pos [2/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 786 of file core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Msk [2/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 787 of file core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Pos [2/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 789 of file core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Msk [2/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 790 of file core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Pos [2/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 793 of file core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Msk [2/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 794 of file core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Pos [2/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 796 of file core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Msk [2/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 797 of file core_armv8mml.h.

◆ SCB_CFSR_STKOF_Pos [2/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 799 of file core_armv8mml.h.

◆ SCB_CFSR_STKOF_Msk [2/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 800 of file core_armv8mml.h.

◆ SCB_CFSR_NOCP_Pos [2/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 802 of file core_armv8mml.h.

◆ SCB_CFSR_NOCP_Msk [2/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 803 of file core_armv8mml.h.

◆ SCB_CFSR_INVPC_Pos [2/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 805 of file core_armv8mml.h.

◆ SCB_CFSR_INVPC_Msk [2/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 806 of file core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Pos [2/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 808 of file core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Msk [2/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 809 of file core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [2/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 811 of file core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [2/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 812 of file core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Pos [2/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 815 of file core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Msk [2/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 816 of file core_armv8mml.h.

◆ SCB_HFSR_FORCED_Pos [2/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 818 of file core_armv8mml.h.

◆ SCB_HFSR_FORCED_Msk [2/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 819 of file core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Pos [2/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 821 of file core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Msk [2/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 822 of file core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Pos [2/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 825 of file core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Msk [2/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 826 of file core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Pos [2/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 828 of file core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Msk [2/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 829 of file core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Pos [2/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 831 of file core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Msk [2/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 832 of file core_armv8mml.h.

◆ SCB_DFSR_BKPT_Pos [2/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 834 of file core_armv8mml.h.

◆ SCB_DFSR_BKPT_Msk [2/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 835 of file core_armv8mml.h.

◆ SCB_DFSR_HALTED_Pos [2/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 837 of file core_armv8mml.h.

◆ SCB_DFSR_HALTED_Msk [2/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 838 of file core_armv8mml.h.

◆ SCB_NSACR_CP11_Pos [2/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 841 of file core_armv8mml.h.

◆ SCB_NSACR_CP11_Msk [2/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 842 of file core_armv8mml.h.

◆ SCB_NSACR_CP10_Pos [2/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 844 of file core_armv8mml.h.

◆ SCB_NSACR_CP10_Msk [2/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 845 of file core_armv8mml.h.

◆ SCB_NSACR_CPn_Pos [1/4]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 847 of file core_armv8mml.h.

◆ SCB_NSACR_CPn_Msk [1/4]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 848 of file core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Pos [2/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 851 of file core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Msk [2/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 852 of file core_armv8mml.h.

◆ SCB_CLIDR_LOC_Pos [2/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 854 of file core_armv8mml.h.

◆ SCB_CLIDR_LOC_Msk [2/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 855 of file core_armv8mml.h.

◆ SCB_CTR_FORMAT_Pos [2/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 858 of file core_armv8mml.h.

◆ SCB_CTR_FORMAT_Msk [2/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 859 of file core_armv8mml.h.

◆ SCB_CTR_CWG_Pos [2/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 861 of file core_armv8mml.h.

◆ SCB_CTR_CWG_Msk [2/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 862 of file core_armv8mml.h.

◆ SCB_CTR_ERG_Pos [2/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 864 of file core_armv8mml.h.

◆ SCB_CTR_ERG_Msk [2/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 865 of file core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Pos [2/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 867 of file core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Msk [2/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 868 of file core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Pos [2/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 870 of file core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Msk [2/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 871 of file core_armv8mml.h.

◆ SCB_CCSIDR_WT_Pos [2/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 874 of file core_armv8mml.h.

◆ SCB_CCSIDR_WT_Msk [2/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 875 of file core_armv8mml.h.

◆ SCB_CCSIDR_WB_Pos [2/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 877 of file core_armv8mml.h.

◆ SCB_CCSIDR_WB_Msk [2/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 878 of file core_armv8mml.h.

◆ SCB_CCSIDR_RA_Pos [2/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 880 of file core_armv8mml.h.

◆ SCB_CCSIDR_RA_Msk [2/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 881 of file core_armv8mml.h.

◆ SCB_CCSIDR_WA_Pos [2/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 883 of file core_armv8mml.h.

◆ SCB_CCSIDR_WA_Msk [2/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 884 of file core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Pos [2/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 886 of file core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Msk [2/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 887 of file core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [2/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 889 of file core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [2/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 890 of file core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Pos [2/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 892 of file core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Msk [2/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 893 of file core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Pos [2/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 896 of file core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Msk [2/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 897 of file core_armv8mml.h.

◆ SCB_CSSELR_IND_Pos [2/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 899 of file core_armv8mml.h.

◆ SCB_CSSELR_IND_Msk [2/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 900 of file core_armv8mml.h.

◆ SCB_STIR_INTID_Pos [2/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 903 of file core_armv8mml.h.

◆ SCB_STIR_INTID_Msk [2/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 904 of file core_armv8mml.h.

◆ SCB_DCISW_WAY_Pos [2/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 907 of file core_armv8mml.h.

◆ SCB_DCISW_WAY_Msk [2/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 908 of file core_armv8mml.h.

◆ SCB_DCISW_SET_Pos [2/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 910 of file core_armv8mml.h.

◆ SCB_DCISW_SET_Msk [2/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 911 of file core_armv8mml.h.

◆ SCB_DCCSW_WAY_Pos [2/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 914 of file core_armv8mml.h.

◆ SCB_DCCSW_WAY_Msk [2/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 915 of file core_armv8mml.h.

◆ SCB_DCCSW_SET_Pos [2/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 917 of file core_armv8mml.h.

◆ SCB_DCCSW_SET_Msk [2/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 918 of file core_armv8mml.h.

◆ SCB_DCCISW_WAY_Pos [2/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 921 of file core_armv8mml.h.

◆ SCB_DCCISW_WAY_Msk [2/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 922 of file core_armv8mml.h.

◆ SCB_DCCISW_SET_Pos [2/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 924 of file core_armv8mml.h.

◆ SCB_DCCISW_SET_Msk [2/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 925 of file core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [4/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [4/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file core_cm0.h.

◆ SCB_CPUID_VARIANT_Pos [4/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 358 of file core_cm0.h.

◆ SCB_CPUID_VARIANT_Msk [4/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [4/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [4/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file core_cm0.h.

◆ SCB_CPUID_PARTNO_Pos [4/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 364 of file core_cm0.h.

◆ SCB_CPUID_PARTNO_Msk [4/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file core_cm0.h.

◆ SCB_CPUID_REVISION_Pos [4/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 367 of file core_cm0.h.

◆ SCB_CPUID_REVISION_Msk [4/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file core_cm0.h.

◆ SCB_ICSR_NMIPENDSET_Pos [4/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 371 of file core_cm0.h.

◆ SCB_ICSR_NMIPENDSET_Msk [4/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 372 of file core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Pos [4/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Msk [4/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Pos [4/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Msk [4/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Pos [4/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Msk [4/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Pos [4/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Msk [4/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [4/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [4/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Pos [4/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Msk [4/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Pos [4/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Msk [4/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Pos [4/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Msk [4/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Pos [4/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Msk [4/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [4/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [4/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Pos [4/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Msk [4/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [4/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [4/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [4/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [4/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file core_cm0.h.

◆ SCB_SCR_SEVONPEND_Pos [4/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file core_cm0.h.

◆ SCB_SCR_SEVONPEND_Msk [4/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Pos [4/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Msk [4/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [4/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [4/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file core_cm0.h.

◆ SCB_CCR_STKALIGN_Pos [1/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 425 of file core_cm0.h.

◆ SCB_CCR_STKALIGN_Msk [1/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [4/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [4/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [4/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [4/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [5/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 373 of file core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [5/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 374 of file core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Pos [5/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 376 of file core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Msk [5/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 377 of file core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [5/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 379 of file core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [5/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 380 of file core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Pos [5/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 382 of file core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Msk [5/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 383 of file core_cm0plus.h.

◆ SCB_CPUID_REVISION_Pos [5/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 385 of file core_cm0plus.h.

◆ SCB_CPUID_REVISION_Msk [5/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 386 of file core_cm0plus.h.

◆ SCB_ICSR_NMIPENDSET_Pos [5/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 389 of file core_cm0plus.h.

◆ SCB_ICSR_NMIPENDSET_Msk [5/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 390 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Pos [5/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 392 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Msk [5/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 393 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Pos [5/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 395 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Msk [5/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 396 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Pos [5/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 398 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Msk [5/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 399 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Pos [5/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 401 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Msk [5/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 402 of file core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [5/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 404 of file core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [5/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 405 of file core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Pos [5/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 407 of file core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Msk [5/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 408 of file core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Pos [5/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 410 of file core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Msk [5/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 411 of file core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Pos [5/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 413 of file core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Msk [5/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 414 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Pos [5/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 423 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Msk [5/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 424 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [5/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 426 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [5/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 427 of file core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Pos [5/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 429 of file core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Msk [5/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 430 of file core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [5/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 432 of file core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [5/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 433 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [5/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 435 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [5/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 436 of file core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Pos [5/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 439 of file core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Msk [5/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 440 of file core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Pos [5/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 442 of file core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Msk [5/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 443 of file core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [5/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 445 of file core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [5/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 446 of file core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Pos [2/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 449 of file core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Msk [2/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 450 of file core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [5/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 452 of file core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [5/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 453 of file core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [5/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 456 of file core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [5/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 457 of file core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [6/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [6/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file core_cm1.h.

◆ SCB_CPUID_VARIANT_Pos [6/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 358 of file core_cm1.h.

◆ SCB_CPUID_VARIANT_Msk [6/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [6/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [6/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file core_cm1.h.

◆ SCB_CPUID_PARTNO_Pos [6/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 364 of file core_cm1.h.

◆ SCB_CPUID_PARTNO_Msk [6/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file core_cm1.h.

◆ SCB_CPUID_REVISION_Pos [6/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 367 of file core_cm1.h.

◆ SCB_CPUID_REVISION_Msk [6/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file core_cm1.h.

◆ SCB_ICSR_NMIPENDSET_Pos [6/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 371 of file core_cm1.h.

◆ SCB_ICSR_NMIPENDSET_Msk [6/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 372 of file core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Pos [6/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Msk [6/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Pos [6/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Msk [6/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Pos [6/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Msk [6/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Pos [6/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Msk [6/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [6/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [6/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Pos [6/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Msk [6/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Pos [6/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Msk [6/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Pos [6/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Msk [6/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Pos [6/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Msk [6/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [6/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [6/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Pos [6/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Msk [6/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [6/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [6/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [6/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [6/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file core_cm1.h.

◆ SCB_SCR_SEVONPEND_Pos [6/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file core_cm1.h.

◆ SCB_SCR_SEVONPEND_Msk [6/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Pos [6/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Msk [6/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [6/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [6/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file core_cm1.h.

◆ SCB_CCR_STKALIGN_Pos [3/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 425 of file core_cm1.h.

◆ SCB_CCR_STKALIGN_Msk [3/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [6/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [6/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [6/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [6/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [7/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 401 of file core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [7/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 402 of file core_cm23.h.

◆ SCB_CPUID_VARIANT_Pos [7/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 404 of file core_cm23.h.

◆ SCB_CPUID_VARIANT_Msk [7/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 405 of file core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [7/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 407 of file core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [7/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 408 of file core_cm23.h.

◆ SCB_CPUID_PARTNO_Pos [7/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 410 of file core_cm23.h.

◆ SCB_CPUID_PARTNO_Msk [7/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 411 of file core_cm23.h.

◆ SCB_CPUID_REVISION_Pos [7/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 413 of file core_cm23.h.

◆ SCB_CPUID_REVISION_Msk [7/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 414 of file core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Pos [4/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 417 of file core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Msk [4/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 418 of file core_cm23.h.

◆ SCB_ICSR_NMIPENDSET_Pos [7/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

Definition at line 420 of file core_cm23.h.

◆ SCB_ICSR_NMIPENDSET_Msk [7/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

Definition at line 421 of file core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Pos [4/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 423 of file core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Msk [4/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 424 of file core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Pos [7/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 426 of file core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Msk [7/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 427 of file core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Pos [7/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 429 of file core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Msk [7/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 430 of file core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Pos [7/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 432 of file core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Msk [7/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 433 of file core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Pos [7/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 435 of file core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Msk [7/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 436 of file core_cm23.h.

◆ SCB_ICSR_STTNS_Pos [4/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 438 of file core_cm23.h.

◆ SCB_ICSR_STTNS_Msk [4/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 439 of file core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [7/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 441 of file core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [7/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 442 of file core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Pos [7/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 444 of file core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Msk [7/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 445 of file core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Pos [7/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 447 of file core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Msk [7/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 448 of file core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Pos [4/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 450 of file core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Msk [4/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 451 of file core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Pos [7/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 453 of file core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Msk [7/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 454 of file core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Pos [7/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 463 of file core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Msk [7/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 464 of file core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [7/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 466 of file core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [7/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 467 of file core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Pos [7/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 469 of file core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Msk [7/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 470 of file core_cm23.h.

◆ SCB_AIRCR_PRIS_Pos [4/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 472 of file core_cm23.h.

◆ SCB_AIRCR_PRIS_Msk [4/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 473 of file core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [4/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 475 of file core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [4/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 476 of file core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [4/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 478 of file core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [4/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 479 of file core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [7/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 481 of file core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [7/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 482 of file core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [7/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 484 of file core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [7/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 485 of file core_cm23.h.

◆ SCB_SCR_SEVONPEND_Pos [7/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 488 of file core_cm23.h.

◆ SCB_SCR_SEVONPEND_Msk [7/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 489 of file core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [4/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 491 of file core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [4/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 492 of file core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Pos [7/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 494 of file core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Msk [7/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 495 of file core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [7/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 497 of file core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [7/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 498 of file core_cm23.h.

◆ SCB_CCR_BP_Pos [4/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

Definition at line 501 of file core_cm23.h.

◆ SCB_CCR_BP_Msk [4/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

Definition at line 502 of file core_cm23.h.

◆ SCB_CCR_IC_Pos [4/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

Definition at line 504 of file core_cm23.h.

◆ SCB_CCR_IC_Msk [4/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

Definition at line 505 of file core_cm23.h.

◆ SCB_CCR_DC_Pos [4/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

Definition at line 507 of file core_cm23.h.

◆ SCB_CCR_DC_Msk [4/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

Definition at line 508 of file core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [4/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 510 of file core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [4/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 511 of file core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Pos [4/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 513 of file core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Msk [4/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 514 of file core_cm23.h.

◆ SCB_CCR_DIV_0_TRP_Pos [4/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 516 of file core_cm23.h.

◆ SCB_CCR_DIV_0_TRP_Msk [4/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 517 of file core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [7/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 519 of file core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [7/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 520 of file core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Pos [4/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 522 of file core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Msk [4/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 523 of file core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [4/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 526 of file core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [4/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 527 of file core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [7/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 529 of file core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [7/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 530 of file core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [4/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 532 of file core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [4/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 533 of file core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Pos [4/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 535 of file core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Msk [4/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 536 of file core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Pos [4/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 538 of file core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Msk [4/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 539 of file core_cm23.h.

◆ SCB_SHCSR_NMIACT_Pos [4/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 541 of file core_cm23.h.

◆ SCB_SHCSR_NMIACT_Msk [4/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 542 of file core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [4/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 544 of file core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [4/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 545 of file core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [8/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 405 of file core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [8/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 406 of file core_cm3.h.

◆ SCB_CPUID_VARIANT_Pos [8/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 408 of file core_cm3.h.

◆ SCB_CPUID_VARIANT_Msk [8/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 409 of file core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [8/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 411 of file core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [8/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 412 of file core_cm3.h.

◆ SCB_CPUID_PARTNO_Pos [8/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 414 of file core_cm3.h.

◆ SCB_CPUID_PARTNO_Msk [8/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 415 of file core_cm3.h.

◆ SCB_CPUID_REVISION_Pos [8/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 417 of file core_cm3.h.

◆ SCB_CPUID_REVISION_Msk [8/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 418 of file core_cm3.h.

◆ SCB_ICSR_NMIPENDSET_Pos [8/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 421 of file core_cm3.h.

◆ SCB_ICSR_NMIPENDSET_Msk [8/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 422 of file core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Pos [8/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Msk [8/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Pos [8/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Msk [8/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Pos [8/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Msk [8/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Pos [8/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Msk [8/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [8/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 436 of file core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [8/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 437 of file core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Pos [8/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 439 of file core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Msk [8/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 440 of file core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Pos [8/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 442 of file core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Msk [8/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 443 of file core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Pos [5/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 445 of file core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Msk [5/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 446 of file core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Pos [8/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 448 of file core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Msk [8/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 449 of file core_cm3.h.

◆ SCB_VTOR_TBLOFF_Pos [3/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 459 of file core_cm3.h.

◆ SCB_VTOR_TBLOFF_Msk [3/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 460 of file core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Pos [8/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 464 of file core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Msk [8/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 465 of file core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [8/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 467 of file core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [8/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 468 of file core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Pos [8/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 470 of file core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Msk [8/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 471 of file core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Pos [3/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 473 of file core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Msk [3/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 474 of file core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [8/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 476 of file core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [8/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 477 of file core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [8/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 479 of file core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [8/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 480 of file core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Pos [1/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 482 of file core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Msk [1/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 483 of file core_cm3.h.

◆ SCB_SCR_SEVONPEND_Pos [8/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file core_cm3.h.

◆ SCB_SCR_SEVONPEND_Msk [8/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Pos [8/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 489 of file core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Msk [8/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 490 of file core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [8/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 492 of file core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [8/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 493 of file core_cm3.h.

◆ SCB_CCR_STKALIGN_Pos [4/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 496 of file core_cm3.h.

◆ SCB_CCR_STKALIGN_Msk [4/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 497 of file core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Pos [5/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 499 of file core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Msk [5/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 500 of file core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Pos [5/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 502 of file core_cm3.h.

◆ SCB_CCR_DIV_0_TRP_Msk [5/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 503 of file core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [8/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 505 of file core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [8/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 506 of file core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Pos [5/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 508 of file core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Msk [5/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 509 of file core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [1/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 511 of file core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [1/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 512 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [3/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 515 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [3/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 516 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [3/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 518 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [3/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 519 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [3/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 521 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [3/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 522 of file core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [8/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 524 of file core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [8/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 525 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [3/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 527 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [3/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 528 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [3/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 530 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [3/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 531 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [3/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 533 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [3/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 534 of file core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [5/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 536 of file core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [5/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 537 of file core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Pos [5/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 539 of file core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Msk [5/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 540 of file core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Pos [3/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 542 of file core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Msk [3/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 543 of file core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Pos [5/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 545 of file core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Msk [5/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 546 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [3/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 548 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [3/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 549 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [3/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 551 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [3/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 552 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [3/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 554 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [3/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 555 of file core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Pos [3/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 558 of file core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Msk [3/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 559 of file core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [3/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 561 of file core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [3/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 562 of file core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [3/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 564 of file core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [3/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 565 of file core_cm3.h.

◆ SCB_CFSR_MMARVALID_Pos [3/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 568 of file core_cm3.h.

◆ SCB_CFSR_MMARVALID_Msk [3/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 569 of file core_cm3.h.

◆ SCB_CFSR_MSTKERR_Pos [3/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 571 of file core_cm3.h.

◆ SCB_CFSR_MSTKERR_Msk [3/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 572 of file core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Pos [3/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 574 of file core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Msk [3/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 575 of file core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Pos [3/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 577 of file core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Msk [3/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 578 of file core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Pos [3/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 580 of file core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Msk [3/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 581 of file core_cm3.h.

◆ SCB_CFSR_BFARVALID_Pos [3/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 584 of file core_cm3.h.

◆ SCB_CFSR_BFARVALID_Msk [3/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 585 of file core_cm3.h.

◆ SCB_CFSR_STKERR_Pos [3/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 587 of file core_cm3.h.

◆ SCB_CFSR_STKERR_Msk [3/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 588 of file core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Pos [3/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 590 of file core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Msk [3/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 591 of file core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Pos [3/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 593 of file core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Msk [3/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 594 of file core_cm3.h.

◆ SCB_CFSR_PRECISERR_Pos [3/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 596 of file core_cm3.h.

◆ SCB_CFSR_PRECISERR_Msk [3/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 597 of file core_cm3.h.

◆ SCB_CFSR_IBUSERR_Pos [3/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 599 of file core_cm3.h.

◆ SCB_CFSR_IBUSERR_Msk [3/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 600 of file core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Pos [3/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 603 of file core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Msk [3/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 604 of file core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Pos [3/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 606 of file core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Msk [3/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 607 of file core_cm3.h.

◆ SCB_CFSR_NOCP_Pos [3/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 609 of file core_cm3.h.

◆ SCB_CFSR_NOCP_Msk [3/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 610 of file core_cm3.h.

◆ SCB_CFSR_INVPC_Pos [3/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 612 of file core_cm3.h.

◆ SCB_CFSR_INVPC_Msk [3/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 613 of file core_cm3.h.

◆ SCB_CFSR_INVSTATE_Pos [3/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 615 of file core_cm3.h.

◆ SCB_CFSR_INVSTATE_Msk [3/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 616 of file core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [3/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 618 of file core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [3/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 619 of file core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Pos [3/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 622 of file core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Msk [3/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 623 of file core_cm3.h.

◆ SCB_HFSR_FORCED_Pos [3/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 625 of file core_cm3.h.

◆ SCB_HFSR_FORCED_Msk [3/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 626 of file core_cm3.h.

◆ SCB_HFSR_VECTTBL_Pos [3/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 628 of file core_cm3.h.

◆ SCB_HFSR_VECTTBL_Msk [3/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 629 of file core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Pos [3/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 632 of file core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Msk [3/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 633 of file core_cm3.h.

◆ SCB_DFSR_VCATCH_Pos [3/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 635 of file core_cm3.h.

◆ SCB_DFSR_VCATCH_Msk [3/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 636 of file core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Pos [3/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 638 of file core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Msk [3/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 639 of file core_cm3.h.

◆ SCB_DFSR_BKPT_Pos [3/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 641 of file core_cm3.h.

◆ SCB_DFSR_BKPT_Msk [3/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 642 of file core_cm3.h.

◆ SCB_DFSR_HALTED_Pos [3/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 644 of file core_cm3.h.

◆ SCB_DFSR_HALTED_Msk [3/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 645 of file core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [9/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 555 of file core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [9/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 556 of file core_cm33.h.

◆ SCB_CPUID_VARIANT_Pos [9/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 558 of file core_cm33.h.

◆ SCB_CPUID_VARIANT_Msk [9/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 559 of file core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [9/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 561 of file core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [9/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 562 of file core_cm33.h.

◆ SCB_CPUID_PARTNO_Pos [9/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 564 of file core_cm33.h.

◆ SCB_CPUID_PARTNO_Msk [9/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 565 of file core_cm33.h.

◆ SCB_CPUID_REVISION_Pos [9/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 567 of file core_cm33.h.

◆ SCB_CPUID_REVISION_Msk [9/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 568 of file core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Pos [5/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 571 of file core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Msk [5/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 572 of file core_cm33.h.

◆ SCB_ICSR_NMIPENDSET_Pos [9/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

Definition at line 574 of file core_cm33.h.

◆ SCB_ICSR_NMIPENDSET_Msk [9/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

Definition at line 575 of file core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Pos [5/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 577 of file core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Msk [5/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 578 of file core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Pos [9/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 580 of file core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Msk [9/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 581 of file core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Pos [9/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 583 of file core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Msk [9/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 584 of file core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Pos [9/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 586 of file core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Msk [9/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 587 of file core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Pos [9/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 589 of file core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Msk [9/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 590 of file core_cm33.h.

◆ SCB_ICSR_STTNS_Pos [5/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 592 of file core_cm33.h.

◆ SCB_ICSR_STTNS_Msk [5/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 593 of file core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [9/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 595 of file core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [9/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 596 of file core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Pos [9/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 598 of file core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Msk [9/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 599 of file core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Pos [9/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 601 of file core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Msk [9/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 602 of file core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Pos [6/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 604 of file core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Msk [6/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 605 of file core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Pos [9/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 607 of file core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Msk [9/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 608 of file core_cm33.h.

◆ SCB_VTOR_TBLOFF_Pos [4/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 611 of file core_cm33.h.

◆ SCB_VTOR_TBLOFF_Msk [4/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 612 of file core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Pos [9/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 615 of file core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Msk [9/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 616 of file core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [9/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 618 of file core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [9/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 619 of file core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Pos [9/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 621 of file core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Msk [9/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 622 of file core_cm33.h.

◆ SCB_AIRCR_PRIS_Pos [5/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 624 of file core_cm33.h.

◆ SCB_AIRCR_PRIS_Msk [5/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 625 of file core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [5/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 627 of file core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [5/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 628 of file core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Pos [4/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 630 of file core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Msk [4/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 631 of file core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [5/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 633 of file core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [5/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 634 of file core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [9/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 636 of file core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [9/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 637 of file core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [9/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 639 of file core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [9/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 640 of file core_cm33.h.

◆ SCB_SCR_SEVONPEND_Pos [9/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 643 of file core_cm33.h.

◆ SCB_SCR_SEVONPEND_Msk [9/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 644 of file core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [5/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 646 of file core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [5/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 647 of file core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Pos [9/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 649 of file core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Msk [9/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 650 of file core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [9/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 652 of file core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [9/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 653 of file core_cm33.h.

◆ SCB_CCR_BP_Pos [5/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

Definition at line 656 of file core_cm33.h.

◆ SCB_CCR_BP_Msk [5/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

Definition at line 657 of file core_cm33.h.

◆ SCB_CCR_IC_Pos [5/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

Definition at line 659 of file core_cm33.h.

◆ SCB_CCR_IC_Msk [5/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

Definition at line 660 of file core_cm33.h.

◆ SCB_CCR_DC_Pos [5/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

Definition at line 662 of file core_cm33.h.

◆ SCB_CCR_DC_Msk [5/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

Definition at line 663 of file core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [5/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 665 of file core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [5/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 666 of file core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Pos [6/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 668 of file core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Msk [6/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 669 of file core_cm33.h.

◆ SCB_CCR_DIV_0_TRP_Pos [6/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 671 of file core_cm33.h.

◆ SCB_CCR_DIV_0_TRP_Msk [6/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 672 of file core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [9/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 674 of file core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [9/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 675 of file core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Pos [6/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 677 of file core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Msk [6/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 678 of file core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [5/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 681 of file core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [5/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 682 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [3/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 684 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [3/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 685 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [3/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 687 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [3/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 688 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [4/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 690 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [4/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 691 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [4/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 693 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [4/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 694 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [4/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 696 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [4/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 697 of file core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [9/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 699 of file core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [9/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 700 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [4/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 702 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [4/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 703 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [4/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 705 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [4/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 706 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [4/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 708 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [4/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 709 of file core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [6/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 711 of file core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [6/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 712 of file core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Pos [6/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 714 of file core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Msk [6/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 715 of file core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Pos [4/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 717 of file core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Msk [4/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 718 of file core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Pos [6/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 720 of file core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Msk [6/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 721 of file core_cm33.h.

◆ SCB_SHCSR_NMIACT_Pos [5/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 723 of file core_cm33.h.

◆ SCB_SHCSR_NMIACT_Msk [5/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 724 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [3/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 726 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [3/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 727 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [4/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 729 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [4/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 730 of file core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [5/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 732 of file core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [5/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 733 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [4/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 735 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [4/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 736 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [4/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 738 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [4/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 739 of file core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Pos [4/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 742 of file core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Msk [4/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 743 of file core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [4/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 745 of file core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [4/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 746 of file core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [4/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 748 of file core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [4/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 749 of file core_cm33.h.

◆ SCB_CFSR_MMARVALID_Pos [4/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 752 of file core_cm33.h.

◆ SCB_CFSR_MMARVALID_Msk [4/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 753 of file core_cm33.h.

◆ SCB_CFSR_MLSPERR_Pos [3/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 755 of file core_cm33.h.

◆ SCB_CFSR_MLSPERR_Msk [3/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 756 of file core_cm33.h.

◆ SCB_CFSR_MSTKERR_Pos [4/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 758 of file core_cm33.h.

◆ SCB_CFSR_MSTKERR_Msk [4/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 759 of file core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Pos [4/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 761 of file core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Msk [4/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 762 of file core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Pos [4/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 764 of file core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Msk [4/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 765 of file core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Pos [4/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 767 of file core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Msk [4/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 768 of file core_cm33.h.

◆ SCB_CFSR_BFARVALID_Pos [4/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 771 of file core_cm33.h.

◆ SCB_CFSR_BFARVALID_Msk [4/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 772 of file core_cm33.h.

◆ SCB_CFSR_LSPERR_Pos [3/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 774 of file core_cm33.h.

◆ SCB_CFSR_LSPERR_Msk [3/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 775 of file core_cm33.h.

◆ SCB_CFSR_STKERR_Pos [4/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 777 of file core_cm33.h.

◆ SCB_CFSR_STKERR_Msk [4/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 778 of file core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Pos [4/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 780 of file core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Msk [4/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 781 of file core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Pos [4/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 783 of file core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Msk [4/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 784 of file core_cm33.h.

◆ SCB_CFSR_PRECISERR_Pos [4/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 786 of file core_cm33.h.

◆ SCB_CFSR_PRECISERR_Msk [4/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 787 of file core_cm33.h.

◆ SCB_CFSR_IBUSERR_Pos [4/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 789 of file core_cm33.h.

◆ SCB_CFSR_IBUSERR_Msk [4/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 790 of file core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Pos [4/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 793 of file core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Msk [4/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 794 of file core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Pos [4/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 796 of file core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Msk [4/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 797 of file core_cm33.h.

◆ SCB_CFSR_STKOF_Pos [3/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 799 of file core_cm33.h.

◆ SCB_CFSR_STKOF_Msk [3/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 800 of file core_cm33.h.

◆ SCB_CFSR_NOCP_Pos [4/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 802 of file core_cm33.h.

◆ SCB_CFSR_NOCP_Msk [4/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 803 of file core_cm33.h.

◆ SCB_CFSR_INVPC_Pos [4/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 805 of file core_cm33.h.

◆ SCB_CFSR_INVPC_Msk [4/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 806 of file core_cm33.h.

◆ SCB_CFSR_INVSTATE_Pos [4/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 808 of file core_cm33.h.

◆ SCB_CFSR_INVSTATE_Msk [4/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 809 of file core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [4/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 811 of file core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [4/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 812 of file core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Pos [4/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 815 of file core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Msk [4/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 816 of file core_cm33.h.

◆ SCB_HFSR_FORCED_Pos [4/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 818 of file core_cm33.h.

◆ SCB_HFSR_FORCED_Msk [4/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 819 of file core_cm33.h.

◆ SCB_HFSR_VECTTBL_Pos [4/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 821 of file core_cm33.h.

◆ SCB_HFSR_VECTTBL_Msk [4/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 822 of file core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Pos [4/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 825 of file core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Msk [4/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 826 of file core_cm33.h.

◆ SCB_DFSR_VCATCH_Pos [4/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 828 of file core_cm33.h.

◆ SCB_DFSR_VCATCH_Msk [4/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 829 of file core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Pos [4/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 831 of file core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Msk [4/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 832 of file core_cm33.h.

◆ SCB_DFSR_BKPT_Pos [4/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 834 of file core_cm33.h.

◆ SCB_DFSR_BKPT_Msk [4/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 835 of file core_cm33.h.

◆ SCB_DFSR_HALTED_Pos [4/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 837 of file core_cm33.h.

◆ SCB_DFSR_HALTED_Msk [4/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 838 of file core_cm33.h.

◆ SCB_NSACR_CP11_Pos [3/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 841 of file core_cm33.h.

◆ SCB_NSACR_CP11_Msk [3/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 842 of file core_cm33.h.

◆ SCB_NSACR_CP10_Pos [3/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 844 of file core_cm33.h.

◆ SCB_NSACR_CP10_Msk [3/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 845 of file core_cm33.h.

◆ SCB_NSACR_CPn_Pos [2/4]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 847 of file core_cm33.h.

◆ SCB_NSACR_CPn_Msk [2/4]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 848 of file core_cm33.h.

◆ SCB_CLIDR_LOUU_Pos [3/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 851 of file core_cm33.h.

◆ SCB_CLIDR_LOUU_Msk [3/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 852 of file core_cm33.h.

◆ SCB_CLIDR_LOC_Pos [3/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 854 of file core_cm33.h.

◆ SCB_CLIDR_LOC_Msk [3/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 855 of file core_cm33.h.

◆ SCB_CTR_FORMAT_Pos [3/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 858 of file core_cm33.h.

◆ SCB_CTR_FORMAT_Msk [3/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 859 of file core_cm33.h.

◆ SCB_CTR_CWG_Pos [3/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 861 of file core_cm33.h.

◆ SCB_CTR_CWG_Msk [3/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 862 of file core_cm33.h.

◆ SCB_CTR_ERG_Pos [3/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 864 of file core_cm33.h.

◆ SCB_CTR_ERG_Msk [3/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 865 of file core_cm33.h.

◆ SCB_CTR_DMINLINE_Pos [3/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 867 of file core_cm33.h.

◆ SCB_CTR_DMINLINE_Msk [3/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 868 of file core_cm33.h.

◆ SCB_CTR_IMINLINE_Pos [3/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 870 of file core_cm33.h.

◆ SCB_CTR_IMINLINE_Msk [3/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 871 of file core_cm33.h.

◆ SCB_CCSIDR_WT_Pos [3/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 874 of file core_cm33.h.

◆ SCB_CCSIDR_WT_Msk [3/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 875 of file core_cm33.h.

◆ SCB_CCSIDR_WB_Pos [3/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 877 of file core_cm33.h.

◆ SCB_CCSIDR_WB_Msk [3/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 878 of file core_cm33.h.

◆ SCB_CCSIDR_RA_Pos [3/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 880 of file core_cm33.h.

◆ SCB_CCSIDR_RA_Msk [3/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 881 of file core_cm33.h.

◆ SCB_CCSIDR_WA_Pos [3/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 883 of file core_cm33.h.

◆ SCB_CCSIDR_WA_Msk [3/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 884 of file core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Pos [3/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 886 of file core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Msk [3/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 887 of file core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [3/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 889 of file core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [3/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 890 of file core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Pos [3/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 892 of file core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Msk [3/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 893 of file core_cm33.h.

◆ SCB_CSSELR_LEVEL_Pos [3/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 896 of file core_cm33.h.

◆ SCB_CSSELR_LEVEL_Msk [3/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 897 of file core_cm33.h.

◆ SCB_CSSELR_IND_Pos [3/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 899 of file core_cm33.h.

◆ SCB_CSSELR_IND_Msk [3/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 900 of file core_cm33.h.

◆ SCB_STIR_INTID_Pos [3/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 903 of file core_cm33.h.

◆ SCB_STIR_INTID_Msk [3/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 904 of file core_cm33.h.

◆ SCB_DCISW_WAY_Pos [3/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 907 of file core_cm33.h.

◆ SCB_DCISW_WAY_Msk [3/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 908 of file core_cm33.h.

◆ SCB_DCISW_SET_Pos [3/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 910 of file core_cm33.h.

◆ SCB_DCISW_SET_Msk [3/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 911 of file core_cm33.h.

◆ SCB_DCCSW_WAY_Pos [3/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 914 of file core_cm33.h.

◆ SCB_DCCSW_WAY_Msk [3/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 915 of file core_cm33.h.

◆ SCB_DCCSW_SET_Pos [3/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 917 of file core_cm33.h.

◆ SCB_DCCSW_SET_Msk [3/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 918 of file core_cm33.h.

◆ SCB_DCCISW_WAY_Pos [3/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 921 of file core_cm33.h.

◆ SCB_DCCISW_WAY_Msk [3/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 922 of file core_cm33.h.

◆ SCB_DCCISW_SET_Pos [3/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 924 of file core_cm33.h.

◆ SCB_DCCISW_SET_Msk [3/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 925 of file core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [10/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 555 of file core_cm35p.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [10/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 556 of file core_cm35p.h.

◆ SCB_CPUID_VARIANT_Pos [10/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 558 of file core_cm35p.h.

◆ SCB_CPUID_VARIANT_Msk [10/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 559 of file core_cm35p.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [10/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 561 of file core_cm35p.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [10/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 562 of file core_cm35p.h.

◆ SCB_CPUID_PARTNO_Pos [10/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 564 of file core_cm35p.h.

◆ SCB_CPUID_PARTNO_Msk [10/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 565 of file core_cm35p.h.

◆ SCB_CPUID_REVISION_Pos [10/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 567 of file core_cm35p.h.

◆ SCB_CPUID_REVISION_Msk [10/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 568 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMISET_Pos [6/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 571 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMISET_Msk [6/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 572 of file core_cm35p.h.

◆ SCB_ICSR_NMIPENDSET_Pos [10/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

Definition at line 574 of file core_cm35p.h.

◆ SCB_ICSR_NMIPENDSET_Msk [10/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

Definition at line 575 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMICLR_Pos [6/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 577 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMICLR_Msk [6/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 578 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVSET_Pos [10/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 580 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVSET_Msk [10/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 581 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVCLR_Pos [10/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 583 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVCLR_Msk [10/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 584 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTSET_Pos [10/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 586 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTSET_Msk [10/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 587 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTCLR_Pos [10/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 589 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTCLR_Msk [10/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 590 of file core_cm35p.h.

◆ SCB_ICSR_STTNS_Pos [6/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 592 of file core_cm35p.h.

◆ SCB_ICSR_STTNS_Msk [6/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 593 of file core_cm35p.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [10/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 595 of file core_cm35p.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [10/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 596 of file core_cm35p.h.

◆ SCB_ICSR_ISRPENDING_Pos [10/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 598 of file core_cm35p.h.

◆ SCB_ICSR_ISRPENDING_Msk [10/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 599 of file core_cm35p.h.

◆ SCB_ICSR_VECTPENDING_Pos [10/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 601 of file core_cm35p.h.

◆ SCB_ICSR_VECTPENDING_Msk [10/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 602 of file core_cm35p.h.

◆ SCB_ICSR_RETTOBASE_Pos [7/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 604 of file core_cm35p.h.

◆ SCB_ICSR_RETTOBASE_Msk [7/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 605 of file core_cm35p.h.

◆ SCB_ICSR_VECTACTIVE_Pos [10/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 607 of file core_cm35p.h.

◆ SCB_ICSR_VECTACTIVE_Msk [10/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 608 of file core_cm35p.h.

◆ SCB_VTOR_TBLOFF_Pos [5/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 611 of file core_cm35p.h.

◆ SCB_VTOR_TBLOFF_Msk [5/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 612 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEY_Pos [10/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 615 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEY_Msk [10/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 616 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [10/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 618 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [10/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 619 of file core_cm35p.h.

◆ SCB_AIRCR_ENDIANESS_Pos [10/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 621 of file core_cm35p.h.

◆ SCB_AIRCR_ENDIANESS_Msk [10/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 622 of file core_cm35p.h.

◆ SCB_AIRCR_PRIS_Pos [6/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 624 of file core_cm35p.h.

◆ SCB_AIRCR_PRIS_Msk [6/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 625 of file core_cm35p.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [6/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 627 of file core_cm35p.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [6/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 628 of file core_cm35p.h.

◆ SCB_AIRCR_PRIGROUP_Pos [5/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 630 of file core_cm35p.h.

◆ SCB_AIRCR_PRIGROUP_Msk [5/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 631 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [6/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 633 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [6/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 634 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [10/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 636 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [10/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 637 of file core_cm35p.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [10/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 639 of file core_cm35p.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [10/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 640 of file core_cm35p.h.

◆ SCB_SCR_SEVONPEND_Pos [10/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 643 of file core_cm35p.h.

◆ SCB_SCR_SEVONPEND_Msk [10/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 644 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [6/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 646 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [6/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 647 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEP_Pos [10/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 649 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEP_Msk [10/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 650 of file core_cm35p.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [10/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 652 of file core_cm35p.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [10/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 653 of file core_cm35p.h.

◆ SCB_CCR_BP_Pos [6/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

Definition at line 656 of file core_cm35p.h.

◆ SCB_CCR_BP_Msk [6/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

Definition at line 657 of file core_cm35p.h.

◆ SCB_CCR_IC_Pos [6/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

Definition at line 659 of file core_cm35p.h.

◆ SCB_CCR_IC_Msk [6/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

Definition at line 660 of file core_cm35p.h.

◆ SCB_CCR_DC_Pos [6/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

Definition at line 662 of file core_cm35p.h.

◆ SCB_CCR_DC_Msk [6/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

Definition at line 663 of file core_cm35p.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [6/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 665 of file core_cm35p.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [6/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 666 of file core_cm35p.h.

◆ SCB_CCR_BFHFNMIGN_Pos [7/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 668 of file core_cm35p.h.

◆ SCB_CCR_BFHFNMIGN_Msk [7/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 669 of file core_cm35p.h.

◆ SCB_CCR_DIV_0_TRP_Pos [7/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 671 of file core_cm35p.h.

◆ SCB_CCR_DIV_0_TRP_Msk [7/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 672 of file core_cm35p.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [10/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 674 of file core_cm35p.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [10/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 675 of file core_cm35p.h.

◆ SCB_CCR_USERSETMPEND_Pos [7/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 677 of file core_cm35p.h.

◆ SCB_CCR_USERSETMPEND_Msk [7/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 678 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [6/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 681 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [6/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 682 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [4/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 684 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [4/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 685 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [4/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 687 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [4/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 688 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [5/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 690 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [5/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 691 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [5/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 693 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [5/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 694 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [5/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 696 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [5/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 697 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [10/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 699 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [10/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 700 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [5/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 702 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [5/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 703 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [5/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 705 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [5/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 706 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [5/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 708 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [5/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 709 of file core_cm35p.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [7/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 711 of file core_cm35p.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [7/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 712 of file core_cm35p.h.

◆ SCB_SHCSR_PENDSVACT_Pos [7/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 714 of file core_cm35p.h.

◆ SCB_SHCSR_PENDSVACT_Msk [7/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 715 of file core_cm35p.h.

◆ SCB_SHCSR_MONITORACT_Pos [5/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 717 of file core_cm35p.h.

◆ SCB_SHCSR_MONITORACT_Msk [5/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 718 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLACT_Pos [7/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 720 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLACT_Msk [7/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 721 of file core_cm35p.h.

◆ SCB_SHCSR_NMIACT_Pos [6/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 723 of file core_cm35p.h.

◆ SCB_SHCSR_NMIACT_Msk [6/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 724 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [4/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 726 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [4/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 727 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [5/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 729 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [5/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 730 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [6/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 732 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [6/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 733 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [5/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 735 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [5/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 736 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [5/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 738 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [5/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 739 of file core_cm35p.h.

◆ SCB_CFSR_USGFAULTSR_Pos [5/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 742 of file core_cm35p.h.

◆ SCB_CFSR_USGFAULTSR_Msk [5/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 743 of file core_cm35p.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [5/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 745 of file core_cm35p.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [5/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 746 of file core_cm35p.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [5/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 748 of file core_cm35p.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [5/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 749 of file core_cm35p.h.

◆ SCB_CFSR_MMARVALID_Pos [5/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 752 of file core_cm35p.h.

◆ SCB_CFSR_MMARVALID_Msk [5/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 753 of file core_cm35p.h.

◆ SCB_CFSR_MLSPERR_Pos [4/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 755 of file core_cm35p.h.

◆ SCB_CFSR_MLSPERR_Msk [4/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 756 of file core_cm35p.h.

◆ SCB_CFSR_MSTKERR_Pos [5/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 758 of file core_cm35p.h.

◆ SCB_CFSR_MSTKERR_Msk [5/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 759 of file core_cm35p.h.

◆ SCB_CFSR_MUNSTKERR_Pos [5/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 761 of file core_cm35p.h.

◆ SCB_CFSR_MUNSTKERR_Msk [5/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 762 of file core_cm35p.h.

◆ SCB_CFSR_DACCVIOL_Pos [5/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 764 of file core_cm35p.h.

◆ SCB_CFSR_DACCVIOL_Msk [5/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 765 of file core_cm35p.h.

◆ SCB_CFSR_IACCVIOL_Pos [5/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 767 of file core_cm35p.h.

◆ SCB_CFSR_IACCVIOL_Msk [5/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 768 of file core_cm35p.h.

◆ SCB_CFSR_BFARVALID_Pos [5/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 771 of file core_cm35p.h.

◆ SCB_CFSR_BFARVALID_Msk [5/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 772 of file core_cm35p.h.

◆ SCB_CFSR_LSPERR_Pos [4/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 774 of file core_cm35p.h.

◆ SCB_CFSR_LSPERR_Msk [4/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 775 of file core_cm35p.h.

◆ SCB_CFSR_STKERR_Pos [5/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 777 of file core_cm35p.h.

◆ SCB_CFSR_STKERR_Msk [5/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 778 of file core_cm35p.h.

◆ SCB_CFSR_UNSTKERR_Pos [5/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 780 of file core_cm35p.h.

◆ SCB_CFSR_UNSTKERR_Msk [5/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 781 of file core_cm35p.h.

◆ SCB_CFSR_IMPRECISERR_Pos [5/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 783 of file core_cm35p.h.

◆ SCB_CFSR_IMPRECISERR_Msk [5/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 784 of file core_cm35p.h.

◆ SCB_CFSR_PRECISERR_Pos [5/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 786 of file core_cm35p.h.

◆ SCB_CFSR_PRECISERR_Msk [5/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 787 of file core_cm35p.h.

◆ SCB_CFSR_IBUSERR_Pos [5/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 789 of file core_cm35p.h.

◆ SCB_CFSR_IBUSERR_Msk [5/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 790 of file core_cm35p.h.

◆ SCB_CFSR_DIVBYZERO_Pos [5/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 793 of file core_cm35p.h.

◆ SCB_CFSR_DIVBYZERO_Msk [5/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 794 of file core_cm35p.h.

◆ SCB_CFSR_UNALIGNED_Pos [5/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 796 of file core_cm35p.h.

◆ SCB_CFSR_UNALIGNED_Msk [5/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 797 of file core_cm35p.h.

◆ SCB_CFSR_STKOF_Pos [4/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 799 of file core_cm35p.h.

◆ SCB_CFSR_STKOF_Msk [4/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 800 of file core_cm35p.h.

◆ SCB_CFSR_NOCP_Pos [5/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 802 of file core_cm35p.h.

◆ SCB_CFSR_NOCP_Msk [5/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 803 of file core_cm35p.h.

◆ SCB_CFSR_INVPC_Pos [5/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 805 of file core_cm35p.h.

◆ SCB_CFSR_INVPC_Msk [5/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 806 of file core_cm35p.h.

◆ SCB_CFSR_INVSTATE_Pos [5/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 808 of file core_cm35p.h.

◆ SCB_CFSR_INVSTATE_Msk [5/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 809 of file core_cm35p.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [5/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 811 of file core_cm35p.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [5/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 812 of file core_cm35p.h.

◆ SCB_HFSR_DEBUGEVT_Pos [5/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 815 of file core_cm35p.h.

◆ SCB_HFSR_DEBUGEVT_Msk [5/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 816 of file core_cm35p.h.

◆ SCB_HFSR_FORCED_Pos [5/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 818 of file core_cm35p.h.

◆ SCB_HFSR_FORCED_Msk [5/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 819 of file core_cm35p.h.

◆ SCB_HFSR_VECTTBL_Pos [5/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 821 of file core_cm35p.h.

◆ SCB_HFSR_VECTTBL_Msk [5/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 822 of file core_cm35p.h.

◆ SCB_DFSR_EXTERNAL_Pos [5/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 825 of file core_cm35p.h.

◆ SCB_DFSR_EXTERNAL_Msk [5/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 826 of file core_cm35p.h.

◆ SCB_DFSR_VCATCH_Pos [5/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 828 of file core_cm35p.h.

◆ SCB_DFSR_VCATCH_Msk [5/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 829 of file core_cm35p.h.

◆ SCB_DFSR_DWTTRAP_Pos [5/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 831 of file core_cm35p.h.

◆ SCB_DFSR_DWTTRAP_Msk [5/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 832 of file core_cm35p.h.

◆ SCB_DFSR_BKPT_Pos [5/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 834 of file core_cm35p.h.

◆ SCB_DFSR_BKPT_Msk [5/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 835 of file core_cm35p.h.

◆ SCB_DFSR_HALTED_Pos [5/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 837 of file core_cm35p.h.

◆ SCB_DFSR_HALTED_Msk [5/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 838 of file core_cm35p.h.

◆ SCB_NSACR_CP11_Pos [4/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 841 of file core_cm35p.h.

◆ SCB_NSACR_CP11_Msk [4/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 842 of file core_cm35p.h.

◆ SCB_NSACR_CP10_Pos [4/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 844 of file core_cm35p.h.

◆ SCB_NSACR_CP10_Msk [4/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 845 of file core_cm35p.h.

◆ SCB_NSACR_CPn_Pos [3/4]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 847 of file core_cm35p.h.

◆ SCB_NSACR_CPn_Msk [3/4]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 848 of file core_cm35p.h.

◆ SCB_CLIDR_LOUU_Pos [4/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 851 of file core_cm35p.h.

◆ SCB_CLIDR_LOUU_Msk [4/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 852 of file core_cm35p.h.

◆ SCB_CLIDR_LOC_Pos [4/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 854 of file core_cm35p.h.

◆ SCB_CLIDR_LOC_Msk [4/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 855 of file core_cm35p.h.

◆ SCB_CTR_FORMAT_Pos [4/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 858 of file core_cm35p.h.

◆ SCB_CTR_FORMAT_Msk [4/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 859 of file core_cm35p.h.

◆ SCB_CTR_CWG_Pos [4/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 861 of file core_cm35p.h.

◆ SCB_CTR_CWG_Msk [4/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 862 of file core_cm35p.h.

◆ SCB_CTR_ERG_Pos [4/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 864 of file core_cm35p.h.

◆ SCB_CTR_ERG_Msk [4/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 865 of file core_cm35p.h.

◆ SCB_CTR_DMINLINE_Pos [4/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 867 of file core_cm35p.h.

◆ SCB_CTR_DMINLINE_Msk [4/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 868 of file core_cm35p.h.

◆ SCB_CTR_IMINLINE_Pos [4/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 870 of file core_cm35p.h.

◆ SCB_CTR_IMINLINE_Msk [4/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 871 of file core_cm35p.h.

◆ SCB_CCSIDR_WT_Pos [4/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 874 of file core_cm35p.h.

◆ SCB_CCSIDR_WT_Msk [4/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 875 of file core_cm35p.h.

◆ SCB_CCSIDR_WB_Pos [4/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 877 of file core_cm35p.h.

◆ SCB_CCSIDR_WB_Msk [4/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 878 of file core_cm35p.h.

◆ SCB_CCSIDR_RA_Pos [4/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 880 of file core_cm35p.h.

◆ SCB_CCSIDR_RA_Msk [4/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 881 of file core_cm35p.h.

◆ SCB_CCSIDR_WA_Pos [4/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 883 of file core_cm35p.h.

◆ SCB_CCSIDR_WA_Msk [4/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 884 of file core_cm35p.h.

◆ SCB_CCSIDR_NUMSETS_Pos [4/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 886 of file core_cm35p.h.

◆ SCB_CCSIDR_NUMSETS_Msk [4/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 887 of file core_cm35p.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [4/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 889 of file core_cm35p.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [4/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 890 of file core_cm35p.h.

◆ SCB_CCSIDR_LINESIZE_Pos [4/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 892 of file core_cm35p.h.

◆ SCB_CCSIDR_LINESIZE_Msk [4/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 893 of file core_cm35p.h.

◆ SCB_CSSELR_LEVEL_Pos [4/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 896 of file core_cm35p.h.

◆ SCB_CSSELR_LEVEL_Msk [4/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 897 of file core_cm35p.h.

◆ SCB_CSSELR_IND_Pos [4/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 899 of file core_cm35p.h.

◆ SCB_CSSELR_IND_Msk [4/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 900 of file core_cm35p.h.

◆ SCB_STIR_INTID_Pos [4/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 903 of file core_cm35p.h.

◆ SCB_STIR_INTID_Msk [4/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 904 of file core_cm35p.h.

◆ SCB_DCISW_WAY_Pos [4/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 907 of file core_cm35p.h.

◆ SCB_DCISW_WAY_Msk [4/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 908 of file core_cm35p.h.

◆ SCB_DCISW_SET_Pos [4/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 910 of file core_cm35p.h.

◆ SCB_DCISW_SET_Msk [4/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 911 of file core_cm35p.h.

◆ SCB_DCCSW_WAY_Pos [4/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 914 of file core_cm35p.h.

◆ SCB_DCCSW_WAY_Msk [4/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 915 of file core_cm35p.h.

◆ SCB_DCCSW_SET_Pos [4/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 917 of file core_cm35p.h.

◆ SCB_DCCSW_SET_Msk [4/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 918 of file core_cm35p.h.

◆ SCB_DCCISW_WAY_Pos [4/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 921 of file core_cm35p.h.

◆ SCB_DCCISW_WAY_Msk [4/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 922 of file core_cm35p.h.

◆ SCB_DCCISW_SET_Pos [4/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 924 of file core_cm35p.h.

◆ SCB_DCCISW_SET_Msk [4/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 925 of file core_cm35p.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [11/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 471 of file core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [11/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 472 of file core_cm4.h.

◆ SCB_CPUID_VARIANT_Pos [11/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 474 of file core_cm4.h.

◆ SCB_CPUID_VARIANT_Msk [11/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 475 of file core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [11/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 477 of file core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [11/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 478 of file core_cm4.h.

◆ SCB_CPUID_PARTNO_Pos [11/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 480 of file core_cm4.h.

◆ SCB_CPUID_PARTNO_Msk [11/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 481 of file core_cm4.h.

◆ SCB_CPUID_REVISION_Pos [11/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 483 of file core_cm4.h.

◆ SCB_CPUID_REVISION_Msk [11/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 484 of file core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Pos [11/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 487 of file core_cm4.h.

◆ SCB_ICSR_NMIPENDSET_Msk [11/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 488 of file core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Pos [11/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 490 of file core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Msk [11/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 491 of file core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Pos [11/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 493 of file core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Msk [11/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 494 of file core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Pos [11/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 496 of file core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Msk [11/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 497 of file core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Pos [11/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 499 of file core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Msk [11/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 500 of file core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [11/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 502 of file core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [11/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 503 of file core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Pos [11/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 505 of file core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Msk [11/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 506 of file core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Pos [11/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 508 of file core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Msk [11/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 509 of file core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Pos [8/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 511 of file core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Msk [8/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 512 of file core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Pos [11/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 514 of file core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Msk [11/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 515 of file core_cm4.h.

◆ SCB_VTOR_TBLOFF_Pos [6/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 518 of file core_cm4.h.

◆ SCB_VTOR_TBLOFF_Msk [6/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 519 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Pos [11/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 522 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Msk [11/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 523 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [11/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 525 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [11/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 526 of file core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Pos [11/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 528 of file core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Msk [11/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 529 of file core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Pos [6/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 531 of file core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Msk [6/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 532 of file core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [11/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 534 of file core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [11/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 535 of file core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [11/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 537 of file core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [11/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 538 of file core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Pos [2/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 540 of file core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Msk [2/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 541 of file core_cm4.h.

◆ SCB_SCR_SEVONPEND_Pos [11/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 544 of file core_cm4.h.

◆ SCB_SCR_SEVONPEND_Msk [11/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 545 of file core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Pos [11/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 547 of file core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Msk [11/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 548 of file core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [11/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 550 of file core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [11/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 551 of file core_cm4.h.

◆ SCB_CCR_STKALIGN_Pos [5/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 554 of file core_cm4.h.

◆ SCB_CCR_STKALIGN_Msk [5/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 555 of file core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Pos [8/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 557 of file core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Msk [8/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 558 of file core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Pos [8/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 560 of file core_cm4.h.

◆ SCB_CCR_DIV_0_TRP_Msk [8/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 561 of file core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [11/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 563 of file core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [11/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 564 of file core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Pos [8/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 566 of file core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Msk [8/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 567 of file core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [2/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 569 of file core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [2/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 570 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [6/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 573 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [6/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 574 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [6/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 576 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [6/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 577 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [6/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 579 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [6/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 580 of file core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [11/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 582 of file core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [11/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 583 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [6/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 585 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [6/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 586 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [6/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 588 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [6/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 589 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [6/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 591 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [6/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 592 of file core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [8/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 594 of file core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [8/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 595 of file core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Pos [8/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 597 of file core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Msk [8/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 598 of file core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Pos [6/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 600 of file core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Msk [6/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 601 of file core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Pos [8/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 603 of file core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Msk [8/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 604 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [6/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 606 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [6/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 607 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [6/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 609 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [6/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 610 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [6/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 612 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [6/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 613 of file core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Pos [6/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 616 of file core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Msk [6/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 617 of file core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [6/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 619 of file core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [6/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 620 of file core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [6/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 622 of file core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [6/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 623 of file core_cm4.h.

◆ SCB_CFSR_MMARVALID_Pos [6/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 626 of file core_cm4.h.

◆ SCB_CFSR_MMARVALID_Msk [6/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 627 of file core_cm4.h.

◆ SCB_CFSR_MLSPERR_Pos [5/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 629 of file core_cm4.h.

◆ SCB_CFSR_MLSPERR_Msk [5/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 630 of file core_cm4.h.

◆ SCB_CFSR_MSTKERR_Pos [6/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 632 of file core_cm4.h.

◆ SCB_CFSR_MSTKERR_Msk [6/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 633 of file core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Pos [6/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 635 of file core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Msk [6/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 636 of file core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Pos [6/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 638 of file core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Msk [6/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 639 of file core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Pos [6/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 641 of file core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Msk [6/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 642 of file core_cm4.h.

◆ SCB_CFSR_BFARVALID_Pos [6/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 645 of file core_cm4.h.

◆ SCB_CFSR_BFARVALID_Msk [6/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 646 of file core_cm4.h.

◆ SCB_CFSR_LSPERR_Pos [5/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 648 of file core_cm4.h.

◆ SCB_CFSR_LSPERR_Msk [5/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 649 of file core_cm4.h.

◆ SCB_CFSR_STKERR_Pos [6/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 651 of file core_cm4.h.

◆ SCB_CFSR_STKERR_Msk [6/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 652 of file core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Pos [6/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 654 of file core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Msk [6/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 655 of file core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Pos [6/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 657 of file core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Msk [6/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 658 of file core_cm4.h.

◆ SCB_CFSR_PRECISERR_Pos [6/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 660 of file core_cm4.h.

◆ SCB_CFSR_PRECISERR_Msk [6/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 661 of file core_cm4.h.

◆ SCB_CFSR_IBUSERR_Pos [6/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 663 of file core_cm4.h.

◆ SCB_CFSR_IBUSERR_Msk [6/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 664 of file core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Pos [6/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 667 of file core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Msk [6/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 668 of file core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Pos [6/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 670 of file core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Msk [6/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 671 of file core_cm4.h.

◆ SCB_CFSR_NOCP_Pos [6/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 673 of file core_cm4.h.

◆ SCB_CFSR_NOCP_Msk [6/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 674 of file core_cm4.h.

◆ SCB_CFSR_INVPC_Pos [6/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 676 of file core_cm4.h.

◆ SCB_CFSR_INVPC_Msk [6/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 677 of file core_cm4.h.

◆ SCB_CFSR_INVSTATE_Pos [6/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 679 of file core_cm4.h.

◆ SCB_CFSR_INVSTATE_Msk [6/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 680 of file core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [6/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 682 of file core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [6/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 683 of file core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Pos [6/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 686 of file core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Msk [6/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 687 of file core_cm4.h.

◆ SCB_HFSR_FORCED_Pos [6/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 689 of file core_cm4.h.

◆ SCB_HFSR_FORCED_Msk [6/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 690 of file core_cm4.h.

◆ SCB_HFSR_VECTTBL_Pos [6/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 692 of file core_cm4.h.

◆ SCB_HFSR_VECTTBL_Msk [6/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 693 of file core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Pos [6/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 696 of file core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Msk [6/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 697 of file core_cm4.h.

◆ SCB_DFSR_VCATCH_Pos [6/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 699 of file core_cm4.h.

◆ SCB_DFSR_VCATCH_Msk [6/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 700 of file core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Pos [6/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 702 of file core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Msk [6/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 703 of file core_cm4.h.

◆ SCB_DFSR_BKPT_Pos [6/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 705 of file core_cm4.h.

◆ SCB_DFSR_BKPT_Msk [6/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 706 of file core_cm4.h.

◆ SCB_DFSR_HALTED_Pos [6/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 708 of file core_cm4.h.

◆ SCB_DFSR_HALTED_Msk [6/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 709 of file core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [12/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 565 of file core_cm55.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [12/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 566 of file core_cm55.h.

◆ SCB_CPUID_VARIANT_Pos [12/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 568 of file core_cm55.h.

◆ SCB_CPUID_VARIANT_Msk [12/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 569 of file core_cm55.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [12/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 571 of file core_cm55.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [12/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 572 of file core_cm55.h.

◆ SCB_CPUID_PARTNO_Pos [12/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 574 of file core_cm55.h.

◆ SCB_CPUID_PARTNO_Msk [12/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 575 of file core_cm55.h.

◆ SCB_CPUID_REVISION_Pos [12/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 577 of file core_cm55.h.

◆ SCB_CPUID_REVISION_Msk [12/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 578 of file core_cm55.h.

◆ SCB_ICSR_PENDNMISET_Pos [7/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 581 of file core_cm55.h.

◆ SCB_ICSR_PENDNMISET_Msk [7/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 582 of file core_cm55.h.

◆ SCB_ICSR_NMIPENDSET_Pos [12/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

Definition at line 584 of file core_cm55.h.

◆ SCB_ICSR_NMIPENDSET_Msk [12/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

Definition at line 585 of file core_cm55.h.

◆ SCB_ICSR_PENDNMICLR_Pos [7/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 587 of file core_cm55.h.

◆ SCB_ICSR_PENDNMICLR_Msk [7/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 588 of file core_cm55.h.

◆ SCB_ICSR_PENDSVSET_Pos [12/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 590 of file core_cm55.h.

◆ SCB_ICSR_PENDSVSET_Msk [12/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 591 of file core_cm55.h.

◆ SCB_ICSR_PENDSVCLR_Pos [12/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 593 of file core_cm55.h.

◆ SCB_ICSR_PENDSVCLR_Msk [12/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 594 of file core_cm55.h.

◆ SCB_ICSR_PENDSTSET_Pos [12/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 596 of file core_cm55.h.

◆ SCB_ICSR_PENDSTSET_Msk [12/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 597 of file core_cm55.h.

◆ SCB_ICSR_PENDSTCLR_Pos [12/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 599 of file core_cm55.h.

◆ SCB_ICSR_PENDSTCLR_Msk [12/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 600 of file core_cm55.h.

◆ SCB_ICSR_STTNS_Pos [7/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 602 of file core_cm55.h.

◆ SCB_ICSR_STTNS_Msk [7/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 603 of file core_cm55.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [12/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 605 of file core_cm55.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [12/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 606 of file core_cm55.h.

◆ SCB_ICSR_ISRPENDING_Pos [12/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 608 of file core_cm55.h.

◆ SCB_ICSR_ISRPENDING_Msk [12/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 609 of file core_cm55.h.

◆ SCB_ICSR_VECTPENDING_Pos [12/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 611 of file core_cm55.h.

◆ SCB_ICSR_VECTPENDING_Msk [12/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 612 of file core_cm55.h.

◆ SCB_ICSR_RETTOBASE_Pos [9/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 614 of file core_cm55.h.

◆ SCB_ICSR_RETTOBASE_Msk [9/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 615 of file core_cm55.h.

◆ SCB_ICSR_VECTACTIVE_Pos [12/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 617 of file core_cm55.h.

◆ SCB_ICSR_VECTACTIVE_Msk [12/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 618 of file core_cm55.h.

◆ SCB_VTOR_TBLOFF_Pos [7/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 621 of file core_cm55.h.

◆ SCB_VTOR_TBLOFF_Msk [7/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 622 of file core_cm55.h.

◆ SCB_AIRCR_VECTKEY_Pos [12/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 625 of file core_cm55.h.

◆ SCB_AIRCR_VECTKEY_Msk [12/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 626 of file core_cm55.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [12/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 628 of file core_cm55.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [12/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 629 of file core_cm55.h.

◆ SCB_AIRCR_ENDIANESS_Pos [12/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 631 of file core_cm55.h.

◆ SCB_AIRCR_ENDIANESS_Msk [12/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 632 of file core_cm55.h.

◆ SCB_AIRCR_PRIS_Pos [7/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 634 of file core_cm55.h.

◆ SCB_AIRCR_PRIS_Msk [7/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 635 of file core_cm55.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [7/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 637 of file core_cm55.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [7/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 638 of file core_cm55.h.

◆ SCB_AIRCR_PRIGROUP_Pos [7/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 640 of file core_cm55.h.

◆ SCB_AIRCR_PRIGROUP_Msk [7/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 641 of file core_cm55.h.

◆ SCB_AIRCR_IESB_Pos [2/3]

#define SCB_AIRCR_IESB_Pos   5U

SCB AIRCR: Implicit ESB Enable Position

Definition at line 643 of file core_cm55.h.

◆ SCB_AIRCR_IESB_Msk [2/3]

#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)

SCB AIRCR: Implicit ESB Enable Mask

Definition at line 644 of file core_cm55.h.

◆ SCB_AIRCR_DIT_Pos [2/3]

#define SCB_AIRCR_DIT_Pos   4U

SCB AIRCR: Data Independent Timing Position

Definition at line 646 of file core_cm55.h.

◆ SCB_AIRCR_DIT_Msk [2/3]

#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)

SCB AIRCR: Data Independent Timing Mask

Definition at line 647 of file core_cm55.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [7/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 649 of file core_cm55.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [7/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 650 of file core_cm55.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [12/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 652 of file core_cm55.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [12/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 653 of file core_cm55.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [12/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 655 of file core_cm55.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [12/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 656 of file core_cm55.h.

◆ SCB_SCR_SEVONPEND_Pos [12/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 659 of file core_cm55.h.

◆ SCB_SCR_SEVONPEND_Msk [12/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 660 of file core_cm55.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [7/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 662 of file core_cm55.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [7/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 663 of file core_cm55.h.

◆ SCB_SCR_SLEEPDEEP_Pos [12/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 665 of file core_cm55.h.

◆ SCB_SCR_SLEEPDEEP_Msk [12/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 666 of file core_cm55.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [12/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 668 of file core_cm55.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [12/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 669 of file core_cm55.h.

◆ SCB_CCR_TRD_Pos [2/3]

#define SCB_CCR_TRD_Pos   20U

SCB CCR: TRD Position

Definition at line 672 of file core_cm55.h.

◆ SCB_CCR_TRD_Msk [2/3]

#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)

SCB CCR: TRD Mask

Definition at line 673 of file core_cm55.h.

◆ SCB_CCR_LOB_Pos [2/3]

#define SCB_CCR_LOB_Pos   19U

SCB CCR: LOB Position

Definition at line 675 of file core_cm55.h.

◆ SCB_CCR_LOB_Msk [2/3]

#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)

SCB CCR: LOB Mask

Definition at line 676 of file core_cm55.h.

◆ SCB_CCR_BP_Pos [7/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

Definition at line 678 of file core_cm55.h.

◆ SCB_CCR_BP_Msk [7/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

Definition at line 679 of file core_cm55.h.

◆ SCB_CCR_IC_Pos [7/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

Definition at line 681 of file core_cm55.h.

◆ SCB_CCR_IC_Msk [7/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

SCB CCR: Instruction cache enable bit Mask

Definition at line 682 of file core_cm55.h.

◆ SCB_CCR_DC_Pos [7/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

SCB CCR: Cache enable bit Position

Definition at line 684 of file core_cm55.h.

◆ SCB_CCR_DC_Msk [7/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

SCB CCR: Cache enable bit Mask

Definition at line 685 of file core_cm55.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [7/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 687 of file core_cm55.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [7/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 688 of file core_cm55.h.

◆ SCB_CCR_BFHFNMIGN_Pos [9/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 690 of file core_cm55.h.

◆ SCB_CCR_BFHFNMIGN_Msk [9/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 691 of file core_cm55.h.

◆ SCB_CCR_DIV_0_TRP_Pos [9/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 693 of file core_cm55.h.

◆ SCB_CCR_DIV_0_TRP_Msk [9/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 694 of file core_cm55.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [12/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 696 of file core_cm55.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [12/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 697 of file core_cm55.h.

◆ SCB_CCR_USERSETMPEND_Pos [9/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 699 of file core_cm55.h.

◆ SCB_CCR_USERSETMPEND_Msk [9/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 700 of file core_cm55.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [7/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 703 of file core_cm55.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [7/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 704 of file core_cm55.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [5/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 706 of file core_cm55.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [5/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 707 of file core_cm55.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [5/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 709 of file core_cm55.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [5/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 710 of file core_cm55.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [7/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 712 of file core_cm55.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [7/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 713 of file core_cm55.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [7/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 715 of file core_cm55.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [7/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 716 of file core_cm55.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [7/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 718 of file core_cm55.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [7/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 719 of file core_cm55.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [12/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 721 of file core_cm55.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [12/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 722 of file core_cm55.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [7/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 724 of file core_cm55.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [7/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 725 of file core_cm55.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [7/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 727 of file core_cm55.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [7/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 728 of file core_cm55.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [7/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 730 of file core_cm55.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [7/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 731 of file core_cm55.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [9/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 733 of file core_cm55.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [9/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 734 of file core_cm55.h.

◆ SCB_SHCSR_PENDSVACT_Pos [9/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 736 of file core_cm55.h.

◆ SCB_SHCSR_PENDSVACT_Msk [9/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 737 of file core_cm55.h.

◆ SCB_SHCSR_MONITORACT_Pos [7/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 739 of file core_cm55.h.

◆ SCB_SHCSR_MONITORACT_Msk [7/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 740 of file core_cm55.h.

◆ SCB_SHCSR_SVCALLACT_Pos [9/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 742 of file core_cm55.h.

◆ SCB_SHCSR_SVCALLACT_Msk [9/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 743 of file core_cm55.h.

◆ SCB_SHCSR_NMIACT_Pos [7/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 745 of file core_cm55.h.

◆ SCB_SHCSR_NMIACT_Msk [7/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 746 of file core_cm55.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [5/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 748 of file core_cm55.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [5/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 749 of file core_cm55.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [7/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 751 of file core_cm55.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [7/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 752 of file core_cm55.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [7/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 754 of file core_cm55.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [7/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 755 of file core_cm55.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [7/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 757 of file core_cm55.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [7/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 758 of file core_cm55.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [7/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 760 of file core_cm55.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [7/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 761 of file core_cm55.h.

◆ SCB_CFSR_USGFAULTSR_Pos [7/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 764 of file core_cm55.h.

◆ SCB_CFSR_USGFAULTSR_Msk [7/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 765 of file core_cm55.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [7/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 767 of file core_cm55.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [7/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 768 of file core_cm55.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [7/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 770 of file core_cm55.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [7/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 771 of file core_cm55.h.

◆ SCB_CFSR_MMARVALID_Pos [7/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 774 of file core_cm55.h.

◆ SCB_CFSR_MMARVALID_Msk [7/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 775 of file core_cm55.h.

◆ SCB_CFSR_MLSPERR_Pos [6/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 777 of file core_cm55.h.

◆ SCB_CFSR_MLSPERR_Msk [6/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 778 of file core_cm55.h.

◆ SCB_CFSR_MSTKERR_Pos [7/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 780 of file core_cm55.h.

◆ SCB_CFSR_MSTKERR_Msk [7/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 781 of file core_cm55.h.

◆ SCB_CFSR_MUNSTKERR_Pos [7/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 783 of file core_cm55.h.

◆ SCB_CFSR_MUNSTKERR_Msk [7/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 784 of file core_cm55.h.

◆ SCB_CFSR_DACCVIOL_Pos [7/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 786 of file core_cm55.h.

◆ SCB_CFSR_DACCVIOL_Msk [7/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 787 of file core_cm55.h.

◆ SCB_CFSR_IACCVIOL_Pos [7/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 789 of file core_cm55.h.

◆ SCB_CFSR_IACCVIOL_Msk [7/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 790 of file core_cm55.h.

◆ SCB_CFSR_BFARVALID_Pos [7/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 793 of file core_cm55.h.

◆ SCB_CFSR_BFARVALID_Msk [7/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 794 of file core_cm55.h.

◆ SCB_CFSR_LSPERR_Pos [6/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 796 of file core_cm55.h.

◆ SCB_CFSR_LSPERR_Msk [6/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 797 of file core_cm55.h.

◆ SCB_CFSR_STKERR_Pos [7/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 799 of file core_cm55.h.

◆ SCB_CFSR_STKERR_Msk [7/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 800 of file core_cm55.h.

◆ SCB_CFSR_UNSTKERR_Pos [7/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 802 of file core_cm55.h.

◆ SCB_CFSR_UNSTKERR_Msk [7/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 803 of file core_cm55.h.

◆ SCB_CFSR_IMPRECISERR_Pos [7/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 805 of file core_cm55.h.

◆ SCB_CFSR_IMPRECISERR_Msk [7/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 806 of file core_cm55.h.

◆ SCB_CFSR_PRECISERR_Pos [7/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 808 of file core_cm55.h.

◆ SCB_CFSR_PRECISERR_Msk [7/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 809 of file core_cm55.h.

◆ SCB_CFSR_IBUSERR_Pos [7/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 811 of file core_cm55.h.

◆ SCB_CFSR_IBUSERR_Msk [7/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 812 of file core_cm55.h.

◆ SCB_CFSR_DIVBYZERO_Pos [7/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 815 of file core_cm55.h.

◆ SCB_CFSR_DIVBYZERO_Msk [7/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 816 of file core_cm55.h.

◆ SCB_CFSR_UNALIGNED_Pos [7/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 818 of file core_cm55.h.

◆ SCB_CFSR_UNALIGNED_Msk [7/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 819 of file core_cm55.h.

◆ SCB_CFSR_STKOF_Pos [5/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 821 of file core_cm55.h.

◆ SCB_CFSR_STKOF_Msk [5/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 822 of file core_cm55.h.

◆ SCB_CFSR_NOCP_Pos [7/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 824 of file core_cm55.h.

◆ SCB_CFSR_NOCP_Msk [7/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 825 of file core_cm55.h.

◆ SCB_CFSR_INVPC_Pos [7/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 827 of file core_cm55.h.

◆ SCB_CFSR_INVPC_Msk [7/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 828 of file core_cm55.h.

◆ SCB_CFSR_INVSTATE_Pos [7/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 830 of file core_cm55.h.

◆ SCB_CFSR_INVSTATE_Msk [7/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 831 of file core_cm55.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [7/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 833 of file core_cm55.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [7/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 834 of file core_cm55.h.

◆ SCB_HFSR_DEBUGEVT_Pos [7/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 837 of file core_cm55.h.

◆ SCB_HFSR_DEBUGEVT_Msk [7/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 838 of file core_cm55.h.

◆ SCB_HFSR_FORCED_Pos [7/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 840 of file core_cm55.h.

◆ SCB_HFSR_FORCED_Msk [7/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 841 of file core_cm55.h.

◆ SCB_HFSR_VECTTBL_Pos [7/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 843 of file core_cm55.h.

◆ SCB_HFSR_VECTTBL_Msk [7/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 844 of file core_cm55.h.

◆ SCB_DFSR_PMU_Pos [2/3]

#define SCB_DFSR_PMU_Pos   5U

SCB DFSR: PMU Position

Definition at line 847 of file core_cm55.h.

◆ SCB_DFSR_PMU_Msk [2/3]

#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)

SCB DFSR: PMU Mask

Definition at line 848 of file core_cm55.h.

◆ SCB_DFSR_EXTERNAL_Pos [7/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 850 of file core_cm55.h.

◆ SCB_DFSR_EXTERNAL_Msk [7/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 851 of file core_cm55.h.

◆ SCB_DFSR_VCATCH_Pos [7/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 853 of file core_cm55.h.

◆ SCB_DFSR_VCATCH_Msk [7/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 854 of file core_cm55.h.

◆ SCB_DFSR_DWTTRAP_Pos [7/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 856 of file core_cm55.h.

◆ SCB_DFSR_DWTTRAP_Msk [7/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 857 of file core_cm55.h.

◆ SCB_DFSR_BKPT_Pos [7/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 859 of file core_cm55.h.

◆ SCB_DFSR_BKPT_Msk [7/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 860 of file core_cm55.h.

◆ SCB_DFSR_HALTED_Pos [7/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 862 of file core_cm55.h.

◆ SCB_DFSR_HALTED_Msk [7/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 863 of file core_cm55.h.

◆ SCB_NSACR_CP11_Pos [5/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 866 of file core_cm55.h.

◆ SCB_NSACR_CP11_Msk [5/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 867 of file core_cm55.h.

◆ SCB_NSACR_CP10_Pos [5/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 869 of file core_cm55.h.

◆ SCB_NSACR_CP10_Msk [5/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 870 of file core_cm55.h.

◆ SCB_NSACR_CP7_Pos [2/3]

#define SCB_NSACR_CP7_Pos   7U

SCB NSACR: CP7 Position

Definition at line 872 of file core_cm55.h.

◆ SCB_NSACR_CP7_Msk [2/3]

#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)

SCB NSACR: CP7 Mask

Definition at line 873 of file core_cm55.h.

◆ SCB_NSACR_CP6_Pos [2/3]

#define SCB_NSACR_CP6_Pos   6U

SCB NSACR: CP6 Position

Definition at line 875 of file core_cm55.h.

◆ SCB_NSACR_CP6_Msk [2/3]

#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)

SCB NSACR: CP6 Mask

Definition at line 876 of file core_cm55.h.

◆ SCB_NSACR_CP5_Pos [2/3]

#define SCB_NSACR_CP5_Pos   5U

SCB NSACR: CP5 Position

Definition at line 878 of file core_cm55.h.

◆ SCB_NSACR_CP5_Msk [2/3]

#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)

SCB NSACR: CP5 Mask

Definition at line 879 of file core_cm55.h.

◆ SCB_NSACR_CP4_Pos [2/3]

#define SCB_NSACR_CP4_Pos   4U

SCB NSACR: CP4 Position

Definition at line 881 of file core_cm55.h.

◆ SCB_NSACR_CP4_Msk [2/3]

#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)

SCB NSACR: CP4 Mask

Definition at line 882 of file core_cm55.h.

◆ SCB_NSACR_CP3_Pos [2/3]

#define SCB_NSACR_CP3_Pos   3U

SCB NSACR: CP3 Position

Definition at line 884 of file core_cm55.h.

◆ SCB_NSACR_CP3_Msk [2/3]

#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)

SCB NSACR: CP3 Mask

Definition at line 885 of file core_cm55.h.

◆ SCB_NSACR_CP2_Pos [2/3]

#define SCB_NSACR_CP2_Pos   2U

SCB NSACR: CP2 Position

Definition at line 887 of file core_cm55.h.

◆ SCB_NSACR_CP2_Msk [2/3]

#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)

SCB NSACR: CP2 Mask

Definition at line 888 of file core_cm55.h.

◆ SCB_NSACR_CP1_Pos [2/3]

#define SCB_NSACR_CP1_Pos   1U

SCB NSACR: CP1 Position

Definition at line 890 of file core_cm55.h.

◆ SCB_NSACR_CP1_Msk [2/3]

#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)

SCB NSACR: CP1 Mask

Definition at line 891 of file core_cm55.h.

◆ SCB_NSACR_CP0_Pos [2/3]

#define SCB_NSACR_CP0_Pos   0U

SCB NSACR: CP0 Position

Definition at line 893 of file core_cm55.h.

◆ SCB_NSACR_CP0_Msk [2/3]

#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)

SCB NSACR: CP0 Mask

Definition at line 894 of file core_cm55.h.

◆ SCB_ID_DFR_UDE_Pos [2/3]

#define SCB_ID_DFR_UDE_Pos   28U

SCB ID_DFR: UDE Position

Definition at line 897 of file core_cm55.h.

◆ SCB_ID_DFR_UDE_Msk [2/3]

#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)

SCB ID_DFR: UDE Mask

Definition at line 898 of file core_cm55.h.

◆ SCB_ID_DFR_MProfDbg_Pos [2/3]

#define SCB_ID_DFR_MProfDbg_Pos   20U

SCB ID_DFR: MProfDbg Position

Definition at line 900 of file core_cm55.h.

◆ SCB_ID_DFR_MProfDbg_Msk [2/3]

#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)

SCB ID_DFR: MProfDbg Mask

Definition at line 901 of file core_cm55.h.

◆ SCB_CLIDR_LOUU_Pos [5/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 904 of file core_cm55.h.

◆ SCB_CLIDR_LOUU_Msk [5/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 905 of file core_cm55.h.

◆ SCB_CLIDR_LOC_Pos [5/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 907 of file core_cm55.h.

◆ SCB_CLIDR_LOC_Msk [5/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 908 of file core_cm55.h.

◆ SCB_CTR_FORMAT_Pos [5/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 911 of file core_cm55.h.

◆ SCB_CTR_FORMAT_Msk [5/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 912 of file core_cm55.h.

◆ SCB_CTR_CWG_Pos [5/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 914 of file core_cm55.h.

◆ SCB_CTR_CWG_Msk [5/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 915 of file core_cm55.h.

◆ SCB_CTR_ERG_Pos [5/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 917 of file core_cm55.h.

◆ SCB_CTR_ERG_Msk [5/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 918 of file core_cm55.h.

◆ SCB_CTR_DMINLINE_Pos [5/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 920 of file core_cm55.h.

◆ SCB_CTR_DMINLINE_Msk [5/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 921 of file core_cm55.h.

◆ SCB_CTR_IMINLINE_Pos [5/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 923 of file core_cm55.h.

◆ SCB_CTR_IMINLINE_Msk [5/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 924 of file core_cm55.h.

◆ SCB_CCSIDR_WT_Pos [5/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 927 of file core_cm55.h.

◆ SCB_CCSIDR_WT_Msk [5/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 928 of file core_cm55.h.

◆ SCB_CCSIDR_WB_Pos [5/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 930 of file core_cm55.h.

◆ SCB_CCSIDR_WB_Msk [5/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 931 of file core_cm55.h.

◆ SCB_CCSIDR_RA_Pos [5/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 933 of file core_cm55.h.

◆ SCB_CCSIDR_RA_Msk [5/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 934 of file core_cm55.h.

◆ SCB_CCSIDR_WA_Pos [5/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 936 of file core_cm55.h.

◆ SCB_CCSIDR_WA_Msk [5/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 937 of file core_cm55.h.

◆ SCB_CCSIDR_NUMSETS_Pos [5/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 939 of file core_cm55.h.

◆ SCB_CCSIDR_NUMSETS_Msk [5/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 940 of file core_cm55.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [5/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 942 of file core_cm55.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [5/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 943 of file core_cm55.h.

◆ SCB_CCSIDR_LINESIZE_Pos [5/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 945 of file core_cm55.h.

◆ SCB_CCSIDR_LINESIZE_Msk [5/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 946 of file core_cm55.h.

◆ SCB_CSSELR_LEVEL_Pos [5/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 949 of file core_cm55.h.

◆ SCB_CSSELR_LEVEL_Msk [5/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 950 of file core_cm55.h.

◆ SCB_CSSELR_IND_Pos [5/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 952 of file core_cm55.h.

◆ SCB_CSSELR_IND_Msk [5/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 953 of file core_cm55.h.

◆ SCB_STIR_INTID_Pos [5/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 956 of file core_cm55.h.

◆ SCB_STIR_INTID_Msk [5/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 957 of file core_cm55.h.

◆ SCB_RFSR_V_Pos [2/3]

#define SCB_RFSR_V_Pos   31U

SCB RFSR: V Position

Definition at line 960 of file core_cm55.h.

◆ SCB_RFSR_V_Msk [2/3]

#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)

SCB RFSR: V Mask

Definition at line 961 of file core_cm55.h.

◆ SCB_RFSR_IS_Pos [2/3]

#define SCB_RFSR_IS_Pos   16U

SCB RFSR: IS Position

Definition at line 963 of file core_cm55.h.

◆ SCB_RFSR_IS_Msk [2/3]

#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)

SCB RFSR: IS Mask

Definition at line 964 of file core_cm55.h.

◆ SCB_RFSR_UET_Pos [2/3]

#define SCB_RFSR_UET_Pos   0U

SCB RFSR: UET Position

Definition at line 966 of file core_cm55.h.

◆ SCB_RFSR_UET_Msk [2/3]

#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)

SCB RFSR: UET Mask

Definition at line 967 of file core_cm55.h.

◆ SCB_DCISW_WAY_Pos [5/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 970 of file core_cm55.h.

◆ SCB_DCISW_WAY_Msk [5/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 971 of file core_cm55.h.

◆ SCB_DCISW_SET_Pos [5/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 973 of file core_cm55.h.

◆ SCB_DCISW_SET_Msk [5/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 974 of file core_cm55.h.

◆ SCB_DCCSW_WAY_Pos [5/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 977 of file core_cm55.h.

◆ SCB_DCCSW_WAY_Msk [5/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 978 of file core_cm55.h.

◆ SCB_DCCSW_SET_Pos [5/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 980 of file core_cm55.h.

◆ SCB_DCCSW_SET_Msk [5/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 981 of file core_cm55.h.

◆ SCB_DCCISW_WAY_Pos [5/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 984 of file core_cm55.h.

◆ SCB_DCCISW_WAY_Msk [5/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 985 of file core_cm55.h.

◆ SCB_DCCISW_SET_Pos [5/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 987 of file core_cm55.h.

◆ SCB_DCCISW_SET_Msk [5/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 988 of file core_cm55.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [13/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 516 of file core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [13/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 517 of file core_cm7.h.

◆ SCB_CPUID_VARIANT_Pos [13/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 519 of file core_cm7.h.

◆ SCB_CPUID_VARIANT_Msk [13/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 520 of file core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [13/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 522 of file core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [13/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 523 of file core_cm7.h.

◆ SCB_CPUID_PARTNO_Pos [13/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 525 of file core_cm7.h.

◆ SCB_CPUID_PARTNO_Msk [13/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 526 of file core_cm7.h.

◆ SCB_CPUID_REVISION_Pos [13/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 528 of file core_cm7.h.

◆ SCB_CPUID_REVISION_Msk [13/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 529 of file core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Pos [13/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 532 of file core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Msk [13/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 533 of file core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Pos [13/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 535 of file core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Msk [13/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 536 of file core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Pos [13/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 538 of file core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Msk [13/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 539 of file core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Pos [13/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 541 of file core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Msk [13/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 542 of file core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Pos [13/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 544 of file core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Msk [13/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 545 of file core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [13/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 547 of file core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [13/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 548 of file core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Pos [13/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 550 of file core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Msk [13/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 551 of file core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Pos [13/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 553 of file core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Msk [13/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 554 of file core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Pos [10/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 556 of file core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Msk [10/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 557 of file core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Pos [13/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 559 of file core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Msk [13/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 560 of file core_cm7.h.

◆ SCB_VTOR_TBLOFF_Pos [8/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 563 of file core_cm7.h.

◆ SCB_VTOR_TBLOFF_Msk [8/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 564 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Pos [13/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 567 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Msk [13/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 568 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [13/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 570 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [13/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 571 of file core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Pos [13/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 573 of file core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Msk [13/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 574 of file core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Pos [8/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 576 of file core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Msk [8/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 577 of file core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [13/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 579 of file core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [13/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 580 of file core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [13/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 582 of file core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [13/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 583 of file core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Pos [3/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 585 of file core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Msk [3/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 586 of file core_cm7.h.

◆ SCB_SCR_SEVONPEND_Pos [13/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 589 of file core_cm7.h.

◆ SCB_SCR_SEVONPEND_Msk [13/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 590 of file core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Pos [13/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 592 of file core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Msk [13/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 593 of file core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [13/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 595 of file core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [13/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 596 of file core_cm7.h.

◆ SCB_CCR_BP_Pos [8/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: Branch prediction enable bit Position

SCB CCR: BP Position

Definition at line 599 of file core_cm7.h.

◆ SCB_CCR_BP_Msk [8/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: Branch prediction enable bit Mask

SCB CCR: BP Mask

Definition at line 600 of file core_cm7.h.

◆ SCB_CCR_IC_Pos [8/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: Instruction cache enable bit Position

SCB CCR: IC Position

Definition at line 602 of file core_cm7.h.

◆ SCB_CCR_IC_Msk [8/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: Instruction cache enable bit Mask

SCB CCR: IC Mask

Definition at line 603 of file core_cm7.h.

◆ SCB_CCR_DC_Pos [8/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: Cache enable bit Position

SCB CCR: DC Position

Definition at line 605 of file core_cm7.h.

◆ SCB_CCR_DC_Msk [8/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: Cache enable bit Mask

SCB CCR: DC Mask

Definition at line 606 of file core_cm7.h.

◆ SCB_CCR_STKALIGN_Pos [6/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 608 of file core_cm7.h.

◆ SCB_CCR_STKALIGN_Msk [6/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 609 of file core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Pos [10/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 611 of file core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Msk [10/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 612 of file core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Pos [10/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 614 of file core_cm7.h.

◆ SCB_CCR_DIV_0_TRP_Msk [10/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 615 of file core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [13/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 617 of file core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [13/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 618 of file core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Pos [10/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 620 of file core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Msk [10/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 621 of file core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [3/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 623 of file core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [3/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 624 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [8/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 627 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [8/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 628 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [8/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 630 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [8/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 631 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [8/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 633 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [8/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 634 of file core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [13/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 636 of file core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [13/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 637 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [8/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 639 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [8/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 640 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [8/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 642 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [8/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 643 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [8/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 645 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [8/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 646 of file core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [10/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 648 of file core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [10/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 649 of file core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Pos [10/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 651 of file core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Msk [10/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 652 of file core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Pos [8/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 654 of file core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Msk [8/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 655 of file core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Pos [10/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 657 of file core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Msk [10/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 658 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [8/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 660 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [8/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 661 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [8/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 663 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [8/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 664 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [8/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 666 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [8/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 667 of file core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Pos [8/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 670 of file core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Msk [8/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 671 of file core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [8/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 673 of file core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [8/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 674 of file core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [8/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 676 of file core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [8/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 677 of file core_cm7.h.

◆ SCB_CFSR_MMARVALID_Pos [8/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 680 of file core_cm7.h.

◆ SCB_CFSR_MMARVALID_Msk [8/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 681 of file core_cm7.h.

◆ SCB_CFSR_MLSPERR_Pos [7/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 683 of file core_cm7.h.

◆ SCB_CFSR_MLSPERR_Msk [7/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 684 of file core_cm7.h.

◆ SCB_CFSR_MSTKERR_Pos [8/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 686 of file core_cm7.h.

◆ SCB_CFSR_MSTKERR_Msk [8/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 687 of file core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Pos [8/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 689 of file core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Msk [8/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 690 of file core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Pos [8/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 692 of file core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Msk [8/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 693 of file core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Pos [8/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 695 of file core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Msk [8/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 696 of file core_cm7.h.

◆ SCB_CFSR_BFARVALID_Pos [8/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 699 of file core_cm7.h.

◆ SCB_CFSR_BFARVALID_Msk [8/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 700 of file core_cm7.h.

◆ SCB_CFSR_LSPERR_Pos [7/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 702 of file core_cm7.h.

◆ SCB_CFSR_LSPERR_Msk [7/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 703 of file core_cm7.h.

◆ SCB_CFSR_STKERR_Pos [8/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 705 of file core_cm7.h.

◆ SCB_CFSR_STKERR_Msk [8/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 706 of file core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Pos [8/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 708 of file core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Msk [8/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 709 of file core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Pos [8/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 711 of file core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Msk [8/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 712 of file core_cm7.h.

◆ SCB_CFSR_PRECISERR_Pos [8/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 714 of file core_cm7.h.

◆ SCB_CFSR_PRECISERR_Msk [8/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 715 of file core_cm7.h.

◆ SCB_CFSR_IBUSERR_Pos [8/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 717 of file core_cm7.h.

◆ SCB_CFSR_IBUSERR_Msk [8/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 718 of file core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Pos [8/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 721 of file core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Msk [8/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 722 of file core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Pos [8/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 724 of file core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Msk [8/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 725 of file core_cm7.h.

◆ SCB_CFSR_NOCP_Pos [8/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 727 of file core_cm7.h.

◆ SCB_CFSR_NOCP_Msk [8/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 728 of file core_cm7.h.

◆ SCB_CFSR_INVPC_Pos [8/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 730 of file core_cm7.h.

◆ SCB_CFSR_INVPC_Msk [8/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 731 of file core_cm7.h.

◆ SCB_CFSR_INVSTATE_Pos [8/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 733 of file core_cm7.h.

◆ SCB_CFSR_INVSTATE_Msk [8/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 734 of file core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [8/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 736 of file core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [8/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 737 of file core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Pos [8/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 740 of file core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Msk [8/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 741 of file core_cm7.h.

◆ SCB_HFSR_FORCED_Pos [8/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 743 of file core_cm7.h.

◆ SCB_HFSR_FORCED_Msk [8/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 744 of file core_cm7.h.

◆ SCB_HFSR_VECTTBL_Pos [8/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 746 of file core_cm7.h.

◆ SCB_HFSR_VECTTBL_Msk [8/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 747 of file core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Pos [8/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 750 of file core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Msk [8/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 751 of file core_cm7.h.

◆ SCB_DFSR_VCATCH_Pos [8/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 753 of file core_cm7.h.

◆ SCB_DFSR_VCATCH_Msk [8/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 754 of file core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Pos [8/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 756 of file core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Msk [8/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 757 of file core_cm7.h.

◆ SCB_DFSR_BKPT_Pos [8/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 759 of file core_cm7.h.

◆ SCB_DFSR_BKPT_Msk [8/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 760 of file core_cm7.h.

◆ SCB_DFSR_HALTED_Pos [8/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 762 of file core_cm7.h.

◆ SCB_DFSR_HALTED_Msk [8/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 763 of file core_cm7.h.

◆ SCB_CLIDR_LOUU_Pos [6/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 766 of file core_cm7.h.

◆ SCB_CLIDR_LOUU_Msk [6/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 767 of file core_cm7.h.

◆ SCB_CLIDR_LOC_Pos [6/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 769 of file core_cm7.h.

◆ SCB_CLIDR_LOC_Msk [6/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 770 of file core_cm7.h.

◆ SCB_CTR_FORMAT_Pos [6/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 773 of file core_cm7.h.

◆ SCB_CTR_FORMAT_Msk [6/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 774 of file core_cm7.h.

◆ SCB_CTR_CWG_Pos [6/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 776 of file core_cm7.h.

◆ SCB_CTR_CWG_Msk [6/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 777 of file core_cm7.h.

◆ SCB_CTR_ERG_Pos [6/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 779 of file core_cm7.h.

◆ SCB_CTR_ERG_Msk [6/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 780 of file core_cm7.h.

◆ SCB_CTR_DMINLINE_Pos [6/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 782 of file core_cm7.h.

◆ SCB_CTR_DMINLINE_Msk [6/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 783 of file core_cm7.h.

◆ SCB_CTR_IMINLINE_Pos [6/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 785 of file core_cm7.h.

◆ SCB_CTR_IMINLINE_Msk [6/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 786 of file core_cm7.h.

◆ SCB_CCSIDR_WT_Pos [6/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 789 of file core_cm7.h.

◆ SCB_CCSIDR_WT_Msk [6/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 790 of file core_cm7.h.

◆ SCB_CCSIDR_WB_Pos [6/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 792 of file core_cm7.h.

◆ SCB_CCSIDR_WB_Msk [6/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 793 of file core_cm7.h.

◆ SCB_CCSIDR_RA_Pos [6/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 795 of file core_cm7.h.

◆ SCB_CCSIDR_RA_Msk [6/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 796 of file core_cm7.h.

◆ SCB_CCSIDR_WA_Pos [6/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 798 of file core_cm7.h.

◆ SCB_CCSIDR_WA_Msk [6/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 799 of file core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Pos [6/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 801 of file core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Msk [6/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 802 of file core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [6/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 804 of file core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [6/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 805 of file core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Pos [6/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 807 of file core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Msk [6/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 808 of file core_cm7.h.

◆ SCB_CSSELR_LEVEL_Pos [6/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 811 of file core_cm7.h.

◆ SCB_CSSELR_LEVEL_Msk [6/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 812 of file core_cm7.h.

◆ SCB_CSSELR_IND_Pos [6/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 814 of file core_cm7.h.

◆ SCB_CSSELR_IND_Msk [6/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 815 of file core_cm7.h.

◆ SCB_STIR_INTID_Pos [6/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 818 of file core_cm7.h.

◆ SCB_STIR_INTID_Msk [6/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 819 of file core_cm7.h.

◆ SCB_DCISW_WAY_Pos [6/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 822 of file core_cm7.h.

◆ SCB_DCISW_WAY_Msk [6/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 823 of file core_cm7.h.

◆ SCB_DCISW_SET_Pos [6/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 825 of file core_cm7.h.

◆ SCB_DCISW_SET_Msk [6/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 826 of file core_cm7.h.

◆ SCB_DCCSW_WAY_Pos [6/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 829 of file core_cm7.h.

◆ SCB_DCCSW_WAY_Msk [6/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 830 of file core_cm7.h.

◆ SCB_DCCSW_SET_Pos [6/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 832 of file core_cm7.h.

◆ SCB_DCCSW_SET_Msk [6/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 833 of file core_cm7.h.

◆ SCB_DCCISW_WAY_Pos [6/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 836 of file core_cm7.h.

◆ SCB_DCCISW_WAY_Msk [6/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 837 of file core_cm7.h.

◆ SCB_DCCISW_SET_Pos [6/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 839 of file core_cm7.h.

◆ SCB_DCCISW_SET_Msk [6/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 840 of file core_cm7.h.

◆ SCB_ITCMCR_SZ_Pos [1/2]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 843 of file core_cm7.h.

◆ SCB_ITCMCR_SZ_Msk [1/2]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 844 of file core_cm7.h.

◆ SCB_ITCMCR_RETEN_Pos

#define SCB_ITCMCR_RETEN_Pos   2U

SCB ITCMCR: RETEN Position

Definition at line 846 of file core_cm7.h.

◆ SCB_ITCMCR_RETEN_Msk

#define SCB_ITCMCR_RETEN_Msk   (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 847 of file core_cm7.h.

◆ SCB_ITCMCR_RMW_Pos

#define SCB_ITCMCR_RMW_Pos   1U

SCB ITCMCR: RMW Position

Definition at line 849 of file core_cm7.h.

◆ SCB_ITCMCR_RMW_Msk

#define SCB_ITCMCR_RMW_Msk   (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 850 of file core_cm7.h.

◆ SCB_ITCMCR_EN_Pos [1/2]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 852 of file core_cm7.h.

◆ SCB_ITCMCR_EN_Msk [1/2]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 853 of file core_cm7.h.

◆ SCB_DTCMCR_SZ_Pos [1/2]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 856 of file core_cm7.h.

◆ SCB_DTCMCR_SZ_Msk [1/2]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 857 of file core_cm7.h.

◆ SCB_DTCMCR_RETEN_Pos

#define SCB_DTCMCR_RETEN_Pos   2U

SCB DTCMCR: RETEN Position

Definition at line 859 of file core_cm7.h.

◆ SCB_DTCMCR_RETEN_Msk

#define SCB_DTCMCR_RETEN_Msk   (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 860 of file core_cm7.h.

◆ SCB_DTCMCR_RMW_Pos

#define SCB_DTCMCR_RMW_Pos   1U

SCB DTCMCR: RMW Position

Definition at line 862 of file core_cm7.h.

◆ SCB_DTCMCR_RMW_Msk

#define SCB_DTCMCR_RMW_Msk   (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 863 of file core_cm7.h.

◆ SCB_DTCMCR_EN_Pos [1/2]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 865 of file core_cm7.h.

◆ SCB_DTCMCR_EN_Msk [1/2]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 866 of file core_cm7.h.

◆ SCB_AHBPCR_SZ_Pos

#define SCB_AHBPCR_SZ_Pos   1U

SCB AHBPCR: SZ Position

Definition at line 869 of file core_cm7.h.

◆ SCB_AHBPCR_SZ_Msk

#define SCB_AHBPCR_SZ_Msk   (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 870 of file core_cm7.h.

◆ SCB_AHBPCR_EN_Pos

#define SCB_AHBPCR_EN_Pos   0U

SCB AHBPCR: EN Position

Definition at line 872 of file core_cm7.h.

◆ SCB_AHBPCR_EN_Msk

#define SCB_AHBPCR_EN_Msk   (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 873 of file core_cm7.h.

◆ SCB_CACR_FORCEWT_Pos [1/2]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 876 of file core_cm7.h.

◆ SCB_CACR_FORCEWT_Msk [1/2]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 877 of file core_cm7.h.

◆ SCB_CACR_ECCEN_Pos

#define SCB_CACR_ECCEN_Pos   1U
Deprecated
SCB CACR: ECCEN Position

Definition at line 879 of file core_cm7.h.

◆ SCB_CACR_ECCEN_Msk

#define SCB_CACR_ECCEN_Msk   (1UL << SCB_CACR_ECCEN_Pos)
Deprecated
SCB CACR: ECCEN Mask

Definition at line 880 of file core_cm7.h.

◆ SCB_CACR_ECCDIS_Pos

#define SCB_CACR_ECCDIS_Pos   1U

SCB CACR: ECCDIS Position

Definition at line 882 of file core_cm7.h.

◆ SCB_CACR_ECCDIS_Msk

#define SCB_CACR_ECCDIS_Msk   (1UL << SCB_CACR_ECCDIS_Pos)

SCB CACR: ECCDIS Mask

Definition at line 883 of file core_cm7.h.

◆ SCB_CACR_SIWT_Pos

#define SCB_CACR_SIWT_Pos   0U

SCB CACR: SIWT Position

Definition at line 885 of file core_cm7.h.

◆ SCB_CACR_SIWT_Msk

#define SCB_CACR_SIWT_Msk   (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 886 of file core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Pos

#define SCB_AHBSCR_INITCOUNT_Pos   11U

SCB AHBSCR: INITCOUNT Position

Definition at line 889 of file core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Msk

#define SCB_AHBSCR_INITCOUNT_Msk   (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 890 of file core_cm7.h.

◆ SCB_AHBSCR_TPRI_Pos

#define SCB_AHBSCR_TPRI_Pos   2U

SCB AHBSCR: TPRI Position

Definition at line 892 of file core_cm7.h.

◆ SCB_AHBSCR_TPRI_Msk

#define SCB_AHBSCR_TPRI_Msk   (0x1FFUL << SCB_AHBSCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 893 of file core_cm7.h.

◆ SCB_AHBSCR_CTL_Pos

#define SCB_AHBSCR_CTL_Pos   0U

SCB AHBSCR: CTL Position

Definition at line 895 of file core_cm7.h.

◆ SCB_AHBSCR_CTL_Msk

#define SCB_AHBSCR_CTL_Msk   (3UL /*<< SCB_AHBSCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 896 of file core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Pos

#define SCB_ABFSR_AXIMTYPE_Pos   8U

SCB ABFSR: AXIMTYPE Position

Definition at line 899 of file core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Msk

#define SCB_ABFSR_AXIMTYPE_Msk   (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 900 of file core_cm7.h.

◆ SCB_ABFSR_EPPB_Pos

#define SCB_ABFSR_EPPB_Pos   4U

SCB ABFSR: EPPB Position

Definition at line 902 of file core_cm7.h.

◆ SCB_ABFSR_EPPB_Msk

#define SCB_ABFSR_EPPB_Msk   (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 903 of file core_cm7.h.

◆ SCB_ABFSR_AXIM_Pos

#define SCB_ABFSR_AXIM_Pos   3U

SCB ABFSR: AXIM Position

Definition at line 905 of file core_cm7.h.

◆ SCB_ABFSR_AXIM_Msk

#define SCB_ABFSR_AXIM_Msk   (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 906 of file core_cm7.h.

◆ SCB_ABFSR_AHBP_Pos

#define SCB_ABFSR_AHBP_Pos   2U

SCB ABFSR: AHBP Position

Definition at line 908 of file core_cm7.h.

◆ SCB_ABFSR_AHBP_Msk

#define SCB_ABFSR_AHBP_Msk   (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 909 of file core_cm7.h.

◆ SCB_ABFSR_DTCM_Pos

#define SCB_ABFSR_DTCM_Pos   1U

SCB ABFSR: DTCM Position

Definition at line 911 of file core_cm7.h.

◆ SCB_ABFSR_DTCM_Msk

#define SCB_ABFSR_DTCM_Msk   (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 912 of file core_cm7.h.

◆ SCB_ABFSR_ITCM_Pos

#define SCB_ABFSR_ITCM_Pos   0U

SCB ABFSR: ITCM Position

Definition at line 914 of file core_cm7.h.

◆ SCB_ABFSR_ITCM_Msk

#define SCB_ABFSR_ITCM_Msk   (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 915 of file core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [14/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 582 of file core_cm85.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [14/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 583 of file core_cm85.h.

◆ SCB_CPUID_VARIANT_Pos [14/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 585 of file core_cm85.h.

◆ SCB_CPUID_VARIANT_Msk [14/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 586 of file core_cm85.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [14/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 588 of file core_cm85.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [14/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 589 of file core_cm85.h.

◆ SCB_CPUID_PARTNO_Pos [14/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 591 of file core_cm85.h.

◆ SCB_CPUID_PARTNO_Msk [14/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 592 of file core_cm85.h.

◆ SCB_CPUID_REVISION_Pos [14/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 594 of file core_cm85.h.

◆ SCB_CPUID_REVISION_Msk [14/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 595 of file core_cm85.h.

◆ SCB_ICSR_PENDNMISET_Pos [8/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 598 of file core_cm85.h.

◆ SCB_ICSR_PENDNMISET_Msk [8/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 599 of file core_cm85.h.

◆ SCB_ICSR_NMIPENDSET_Pos [14/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

SCB ICSR: NMIPENDSET Position

Definition at line 601 of file core_cm85.h.

◆ SCB_ICSR_NMIPENDSET_Msk [14/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

SCB ICSR: NMIPENDSET Mask

Definition at line 602 of file core_cm85.h.

◆ SCB_ICSR_PENDNMICLR_Pos [8/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 604 of file core_cm85.h.

◆ SCB_ICSR_PENDNMICLR_Msk [8/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 605 of file core_cm85.h.

◆ SCB_ICSR_PENDSVSET_Pos [14/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 607 of file core_cm85.h.

◆ SCB_ICSR_PENDSVSET_Msk [14/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 608 of file core_cm85.h.

◆ SCB_ICSR_PENDSVCLR_Pos [14/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 610 of file core_cm85.h.

◆ SCB_ICSR_PENDSVCLR_Msk [14/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 611 of file core_cm85.h.

◆ SCB_ICSR_PENDSTSET_Pos [14/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 613 of file core_cm85.h.

◆ SCB_ICSR_PENDSTSET_Msk [14/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 614 of file core_cm85.h.

◆ SCB_ICSR_PENDSTCLR_Pos [14/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 616 of file core_cm85.h.

◆ SCB_ICSR_PENDSTCLR_Msk [14/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 617 of file core_cm85.h.

◆ SCB_ICSR_STTNS_Pos [8/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 619 of file core_cm85.h.

◆ SCB_ICSR_STTNS_Msk [8/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 620 of file core_cm85.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [14/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 622 of file core_cm85.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [14/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 623 of file core_cm85.h.

◆ SCB_ICSR_ISRPENDING_Pos [14/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 625 of file core_cm85.h.

◆ SCB_ICSR_ISRPENDING_Msk [14/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 626 of file core_cm85.h.

◆ SCB_ICSR_VECTPENDING_Pos [14/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 628 of file core_cm85.h.

◆ SCB_ICSR_VECTPENDING_Msk [14/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 629 of file core_cm85.h.

◆ SCB_ICSR_RETTOBASE_Pos [11/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 631 of file core_cm85.h.

◆ SCB_ICSR_RETTOBASE_Msk [11/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 632 of file core_cm85.h.

◆ SCB_ICSR_VECTACTIVE_Pos [14/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 634 of file core_cm85.h.

◆ SCB_ICSR_VECTACTIVE_Msk [14/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 635 of file core_cm85.h.

◆ SCB_VTOR_TBLOFF_Pos [9/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 638 of file core_cm85.h.

◆ SCB_VTOR_TBLOFF_Msk [9/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 639 of file core_cm85.h.

◆ SCB_AIRCR_VECTKEY_Pos [14/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 642 of file core_cm85.h.

◆ SCB_AIRCR_VECTKEY_Msk [14/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 643 of file core_cm85.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [14/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 645 of file core_cm85.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [14/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 646 of file core_cm85.h.

◆ SCB_AIRCR_ENDIANESS_Pos [14/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 648 of file core_cm85.h.

◆ SCB_AIRCR_ENDIANESS_Msk [14/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 649 of file core_cm85.h.

◆ SCB_AIRCR_PRIS_Pos [8/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 651 of file core_cm85.h.

◆ SCB_AIRCR_PRIS_Msk [8/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 652 of file core_cm85.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [8/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 654 of file core_cm85.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [8/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 655 of file core_cm85.h.

◆ SCB_AIRCR_PRIGROUP_Pos [9/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 657 of file core_cm85.h.

◆ SCB_AIRCR_PRIGROUP_Msk [9/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 658 of file core_cm85.h.

◆ SCB_AIRCR_IESB_Pos [3/3]

#define SCB_AIRCR_IESB_Pos   5U

SCB AIRCR: Implicit ESB Enable Position

Definition at line 660 of file core_cm85.h.

◆ SCB_AIRCR_IESB_Msk [3/3]

#define SCB_AIRCR_IESB_Msk   (1UL << SCB_AIRCR_IESB_Pos)

SCB AIRCR: Implicit ESB Enable Mask

Definition at line 661 of file core_cm85.h.

◆ SCB_AIRCR_DIT_Pos [3/3]

#define SCB_AIRCR_DIT_Pos   4U

SCB AIRCR: Data Independent Timing Position

Definition at line 663 of file core_cm85.h.

◆ SCB_AIRCR_DIT_Msk [3/3]

#define SCB_AIRCR_DIT_Msk   (1UL << SCB_AIRCR_DIT_Pos)

SCB AIRCR: Data Independent Timing Mask

Definition at line 664 of file core_cm85.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [8/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 666 of file core_cm85.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [8/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 667 of file core_cm85.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [14/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 669 of file core_cm85.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [14/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 670 of file core_cm85.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [14/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 672 of file core_cm85.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [14/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 673 of file core_cm85.h.

◆ SCB_SCR_SEVONPEND_Pos [14/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 676 of file core_cm85.h.

◆ SCB_SCR_SEVONPEND_Msk [14/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 677 of file core_cm85.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [8/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 679 of file core_cm85.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [8/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 680 of file core_cm85.h.

◆ SCB_SCR_SLEEPDEEP_Pos [14/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 682 of file core_cm85.h.

◆ SCB_SCR_SLEEPDEEP_Msk [14/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 683 of file core_cm85.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [14/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 685 of file core_cm85.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [14/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 686 of file core_cm85.h.

◆ SCB_CCR_TRD_Pos [3/3]

#define SCB_CCR_TRD_Pos   20U

SCB CCR: TRD Position

Definition at line 689 of file core_cm85.h.

◆ SCB_CCR_TRD_Msk [3/3]

#define SCB_CCR_TRD_Msk   (1UL << SCB_CCR_TRD_Pos)

SCB CCR: TRD Mask

Definition at line 690 of file core_cm85.h.

◆ SCB_CCR_LOB_Pos [3/3]

#define SCB_CCR_LOB_Pos   19U

SCB CCR: LOB Position

Definition at line 692 of file core_cm85.h.

◆ SCB_CCR_LOB_Msk [3/3]

#define SCB_CCR_LOB_Msk   (1UL << SCB_CCR_LOB_Pos)

SCB CCR: LOB Mask

Definition at line 693 of file core_cm85.h.

◆ SCB_CCR_BP_Pos [9/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 695 of file core_cm85.h.

◆ SCB_CCR_BP_Msk [9/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 696 of file core_cm85.h.

◆ SCB_CCR_IC_Pos [9/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 698 of file core_cm85.h.

◆ SCB_CCR_IC_Msk [9/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 699 of file core_cm85.h.

◆ SCB_CCR_DC_Pos [9/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 701 of file core_cm85.h.

◆ SCB_CCR_DC_Msk [9/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 702 of file core_cm85.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [8/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 704 of file core_cm85.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [8/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 705 of file core_cm85.h.

◆ SCB_CCR_BFHFNMIGN_Pos [11/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 707 of file core_cm85.h.

◆ SCB_CCR_BFHFNMIGN_Msk [11/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 708 of file core_cm85.h.

◆ SCB_CCR_DIV_0_TRP_Pos [11/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 710 of file core_cm85.h.

◆ SCB_CCR_DIV_0_TRP_Msk [11/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 711 of file core_cm85.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [14/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 713 of file core_cm85.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [14/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 714 of file core_cm85.h.

◆ SCB_CCR_USERSETMPEND_Pos [11/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 716 of file core_cm85.h.

◆ SCB_CCR_USERSETMPEND_Msk [11/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 717 of file core_cm85.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [8/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 720 of file core_cm85.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [8/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 721 of file core_cm85.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [6/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 723 of file core_cm85.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [6/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 724 of file core_cm85.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [6/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 726 of file core_cm85.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [6/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 727 of file core_cm85.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [9/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 729 of file core_cm85.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [9/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 730 of file core_cm85.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [9/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 732 of file core_cm85.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [9/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 733 of file core_cm85.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [9/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 735 of file core_cm85.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [9/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 736 of file core_cm85.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [14/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 738 of file core_cm85.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [14/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 739 of file core_cm85.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [9/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 741 of file core_cm85.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [9/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 742 of file core_cm85.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [9/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 744 of file core_cm85.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [9/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 745 of file core_cm85.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [9/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 747 of file core_cm85.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [9/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 748 of file core_cm85.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [11/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 750 of file core_cm85.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [11/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 751 of file core_cm85.h.

◆ SCB_SHCSR_PENDSVACT_Pos [11/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 753 of file core_cm85.h.

◆ SCB_SHCSR_PENDSVACT_Msk [11/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 754 of file core_cm85.h.

◆ SCB_SHCSR_MONITORACT_Pos [9/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 756 of file core_cm85.h.

◆ SCB_SHCSR_MONITORACT_Msk [9/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 757 of file core_cm85.h.

◆ SCB_SHCSR_SVCALLACT_Pos [11/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 759 of file core_cm85.h.

◆ SCB_SHCSR_SVCALLACT_Msk [11/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 760 of file core_cm85.h.

◆ SCB_SHCSR_NMIACT_Pos [8/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 762 of file core_cm85.h.

◆ SCB_SHCSR_NMIACT_Msk [8/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 763 of file core_cm85.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [6/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 765 of file core_cm85.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [6/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 766 of file core_cm85.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [9/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 768 of file core_cm85.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [9/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 769 of file core_cm85.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [8/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 771 of file core_cm85.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [8/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 772 of file core_cm85.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [9/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 774 of file core_cm85.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [9/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 775 of file core_cm85.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [9/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 777 of file core_cm85.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [9/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 778 of file core_cm85.h.

◆ SCB_CFSR_USGFAULTSR_Pos [9/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 781 of file core_cm85.h.

◆ SCB_CFSR_USGFAULTSR_Msk [9/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 782 of file core_cm85.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [9/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 784 of file core_cm85.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [9/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 785 of file core_cm85.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [9/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 787 of file core_cm85.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [9/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 788 of file core_cm85.h.

◆ SCB_CFSR_MMARVALID_Pos [9/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 791 of file core_cm85.h.

◆ SCB_CFSR_MMARVALID_Msk [9/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 792 of file core_cm85.h.

◆ SCB_CFSR_MLSPERR_Pos [8/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 794 of file core_cm85.h.

◆ SCB_CFSR_MLSPERR_Msk [8/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 795 of file core_cm85.h.

◆ SCB_CFSR_MSTKERR_Pos [9/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 797 of file core_cm85.h.

◆ SCB_CFSR_MSTKERR_Msk [9/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 798 of file core_cm85.h.

◆ SCB_CFSR_MUNSTKERR_Pos [9/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 800 of file core_cm85.h.

◆ SCB_CFSR_MUNSTKERR_Msk [9/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 801 of file core_cm85.h.

◆ SCB_CFSR_DACCVIOL_Pos [9/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 803 of file core_cm85.h.

◆ SCB_CFSR_DACCVIOL_Msk [9/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 804 of file core_cm85.h.

◆ SCB_CFSR_IACCVIOL_Pos [9/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 806 of file core_cm85.h.

◆ SCB_CFSR_IACCVIOL_Msk [9/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 807 of file core_cm85.h.

◆ SCB_CFSR_BFARVALID_Pos [9/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 810 of file core_cm85.h.

◆ SCB_CFSR_BFARVALID_Msk [9/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 811 of file core_cm85.h.

◆ SCB_CFSR_LSPERR_Pos [8/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 813 of file core_cm85.h.

◆ SCB_CFSR_LSPERR_Msk [8/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 814 of file core_cm85.h.

◆ SCB_CFSR_STKERR_Pos [9/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 816 of file core_cm85.h.

◆ SCB_CFSR_STKERR_Msk [9/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 817 of file core_cm85.h.

◆ SCB_CFSR_UNSTKERR_Pos [9/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 819 of file core_cm85.h.

◆ SCB_CFSR_UNSTKERR_Msk [9/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 820 of file core_cm85.h.

◆ SCB_CFSR_IMPRECISERR_Pos [9/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 822 of file core_cm85.h.

◆ SCB_CFSR_IMPRECISERR_Msk [9/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 823 of file core_cm85.h.

◆ SCB_CFSR_PRECISERR_Pos [9/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 825 of file core_cm85.h.

◆ SCB_CFSR_PRECISERR_Msk [9/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 826 of file core_cm85.h.

◆ SCB_CFSR_IBUSERR_Pos [9/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 828 of file core_cm85.h.

◆ SCB_CFSR_IBUSERR_Msk [9/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 829 of file core_cm85.h.

◆ SCB_CFSR_DIVBYZERO_Pos [9/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 832 of file core_cm85.h.

◆ SCB_CFSR_DIVBYZERO_Msk [9/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 833 of file core_cm85.h.

◆ SCB_CFSR_UNALIGNED_Pos [9/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 835 of file core_cm85.h.

◆ SCB_CFSR_UNALIGNED_Msk [9/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 836 of file core_cm85.h.

◆ SCB_CFSR_STKOF_Pos [6/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 838 of file core_cm85.h.

◆ SCB_CFSR_STKOF_Msk [6/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 839 of file core_cm85.h.

◆ SCB_CFSR_NOCP_Pos [9/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 841 of file core_cm85.h.

◆ SCB_CFSR_NOCP_Msk [9/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 842 of file core_cm85.h.

◆ SCB_CFSR_INVPC_Pos [9/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 844 of file core_cm85.h.

◆ SCB_CFSR_INVPC_Msk [9/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 845 of file core_cm85.h.

◆ SCB_CFSR_INVSTATE_Pos [9/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 847 of file core_cm85.h.

◆ SCB_CFSR_INVSTATE_Msk [9/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 848 of file core_cm85.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [9/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 850 of file core_cm85.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [9/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 851 of file core_cm85.h.

◆ SCB_HFSR_DEBUGEVT_Pos [9/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 854 of file core_cm85.h.

◆ SCB_HFSR_DEBUGEVT_Msk [9/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 855 of file core_cm85.h.

◆ SCB_HFSR_FORCED_Pos [9/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 857 of file core_cm85.h.

◆ SCB_HFSR_FORCED_Msk [9/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 858 of file core_cm85.h.

◆ SCB_HFSR_VECTTBL_Pos [9/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 860 of file core_cm85.h.

◆ SCB_HFSR_VECTTBL_Msk [9/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 861 of file core_cm85.h.

◆ SCB_DFSR_PMU_Pos [3/3]

#define SCB_DFSR_PMU_Pos   5U

SCB DFSR: PMU Position

Definition at line 864 of file core_cm85.h.

◆ SCB_DFSR_PMU_Msk [3/3]

#define SCB_DFSR_PMU_Msk   (1UL << SCB_DFSR_PMU_Pos)

SCB DFSR: PMU Mask

Definition at line 865 of file core_cm85.h.

◆ SCB_DFSR_EXTERNAL_Pos [9/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 867 of file core_cm85.h.

◆ SCB_DFSR_EXTERNAL_Msk [9/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 868 of file core_cm85.h.

◆ SCB_DFSR_VCATCH_Pos [9/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 870 of file core_cm85.h.

◆ SCB_DFSR_VCATCH_Msk [9/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 871 of file core_cm85.h.

◆ SCB_DFSR_DWTTRAP_Pos [9/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 873 of file core_cm85.h.

◆ SCB_DFSR_DWTTRAP_Msk [9/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 874 of file core_cm85.h.

◆ SCB_DFSR_BKPT_Pos [9/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 876 of file core_cm85.h.

◆ SCB_DFSR_BKPT_Msk [9/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 877 of file core_cm85.h.

◆ SCB_DFSR_HALTED_Pos [9/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 879 of file core_cm85.h.

◆ SCB_DFSR_HALTED_Msk [9/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 880 of file core_cm85.h.

◆ SCB_NSACR_CP11_Pos [6/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 883 of file core_cm85.h.

◆ SCB_NSACR_CP11_Msk [6/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 884 of file core_cm85.h.

◆ SCB_NSACR_CP10_Pos [6/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 886 of file core_cm85.h.

◆ SCB_NSACR_CP10_Msk [6/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 887 of file core_cm85.h.

◆ SCB_NSACR_CP7_Pos [3/3]

#define SCB_NSACR_CP7_Pos   7U

SCB NSACR: CP7 Position

Definition at line 889 of file core_cm85.h.

◆ SCB_NSACR_CP7_Msk [3/3]

#define SCB_NSACR_CP7_Msk   (1UL << SCB_NSACR_CP7_Pos)

SCB NSACR: CP7 Mask

Definition at line 890 of file core_cm85.h.

◆ SCB_NSACR_CP6_Pos [3/3]

#define SCB_NSACR_CP6_Pos   6U

SCB NSACR: CP6 Position

Definition at line 892 of file core_cm85.h.

◆ SCB_NSACR_CP6_Msk [3/3]

#define SCB_NSACR_CP6_Msk   (1UL << SCB_NSACR_CP6_Pos)

SCB NSACR: CP6 Mask

Definition at line 893 of file core_cm85.h.

◆ SCB_NSACR_CP5_Pos [3/3]

#define SCB_NSACR_CP5_Pos   5U

SCB NSACR: CP5 Position

Definition at line 895 of file core_cm85.h.

◆ SCB_NSACR_CP5_Msk [3/3]

#define SCB_NSACR_CP5_Msk   (1UL << SCB_NSACR_CP5_Pos)

SCB NSACR: CP5 Mask

Definition at line 896 of file core_cm85.h.

◆ SCB_NSACR_CP4_Pos [3/3]

#define SCB_NSACR_CP4_Pos   4U

SCB NSACR: CP4 Position

Definition at line 898 of file core_cm85.h.

◆ SCB_NSACR_CP4_Msk [3/3]

#define SCB_NSACR_CP4_Msk   (1UL << SCB_NSACR_CP4_Pos)

SCB NSACR: CP4 Mask

Definition at line 899 of file core_cm85.h.

◆ SCB_NSACR_CP3_Pos [3/3]

#define SCB_NSACR_CP3_Pos   3U

SCB NSACR: CP3 Position

Definition at line 901 of file core_cm85.h.

◆ SCB_NSACR_CP3_Msk [3/3]

#define SCB_NSACR_CP3_Msk   (1UL << SCB_NSACR_CP3_Pos)

SCB NSACR: CP3 Mask

Definition at line 902 of file core_cm85.h.

◆ SCB_NSACR_CP2_Pos [3/3]

#define SCB_NSACR_CP2_Pos   2U

SCB NSACR: CP2 Position

Definition at line 904 of file core_cm85.h.

◆ SCB_NSACR_CP2_Msk [3/3]

#define SCB_NSACR_CP2_Msk   (1UL << SCB_NSACR_CP2_Pos)

SCB NSACR: CP2 Mask

Definition at line 905 of file core_cm85.h.

◆ SCB_NSACR_CP1_Pos [3/3]

#define SCB_NSACR_CP1_Pos   1U

SCB NSACR: CP1 Position

Definition at line 907 of file core_cm85.h.

◆ SCB_NSACR_CP1_Msk [3/3]

#define SCB_NSACR_CP1_Msk   (1UL << SCB_NSACR_CP1_Pos)

SCB NSACR: CP1 Mask

Definition at line 908 of file core_cm85.h.

◆ SCB_NSACR_CP0_Pos [3/3]

#define SCB_NSACR_CP0_Pos   0U

SCB NSACR: CP0 Position

Definition at line 910 of file core_cm85.h.

◆ SCB_NSACR_CP0_Msk [3/3]

#define SCB_NSACR_CP0_Msk   (1UL /*<< SCB_NSACR_CP0_Pos*/)

SCB NSACR: CP0 Mask

Definition at line 911 of file core_cm85.h.

◆ SCB_ID_DFR_UDE_Pos [3/3]

#define SCB_ID_DFR_UDE_Pos   28U

SCB ID_DFR: UDE Position

Definition at line 914 of file core_cm85.h.

◆ SCB_ID_DFR_UDE_Msk [3/3]

#define SCB_ID_DFR_UDE_Msk   (0xFUL << SCB_ID_DFR_UDE_Pos)

SCB ID_DFR: UDE Mask

Definition at line 915 of file core_cm85.h.

◆ SCB_ID_DFR_MProfDbg_Pos [3/3]

#define SCB_ID_DFR_MProfDbg_Pos   20U

SCB ID_DFR: MProfDbg Position

Definition at line 917 of file core_cm85.h.

◆ SCB_ID_DFR_MProfDbg_Msk [3/3]

#define SCB_ID_DFR_MProfDbg_Msk   (0xFUL << SCB_ID_DFR_MProfDbg_Pos)

SCB ID_DFR: MProfDbg Mask

Definition at line 918 of file core_cm85.h.

◆ SCB_CLIDR_LOUU_Pos [7/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 921 of file core_cm85.h.

◆ SCB_CLIDR_LOUU_Msk [7/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 922 of file core_cm85.h.

◆ SCB_CLIDR_LOC_Pos [7/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 924 of file core_cm85.h.

◆ SCB_CLIDR_LOC_Msk [7/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 925 of file core_cm85.h.

◆ SCB_CTR_FORMAT_Pos [7/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 928 of file core_cm85.h.

◆ SCB_CTR_FORMAT_Msk [7/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 929 of file core_cm85.h.

◆ SCB_CTR_CWG_Pos [7/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 931 of file core_cm85.h.

◆ SCB_CTR_CWG_Msk [7/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 932 of file core_cm85.h.

◆ SCB_CTR_ERG_Pos [7/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 934 of file core_cm85.h.

◆ SCB_CTR_ERG_Msk [7/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 935 of file core_cm85.h.

◆ SCB_CTR_DMINLINE_Pos [7/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 937 of file core_cm85.h.

◆ SCB_CTR_DMINLINE_Msk [7/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 938 of file core_cm85.h.

◆ SCB_CTR_IMINLINE_Pos [7/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 940 of file core_cm85.h.

◆ SCB_CTR_IMINLINE_Msk [7/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 941 of file core_cm85.h.

◆ SCB_CCSIDR_WT_Pos [7/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 944 of file core_cm85.h.

◆ SCB_CCSIDR_WT_Msk [7/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 945 of file core_cm85.h.

◆ SCB_CCSIDR_WB_Pos [7/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 947 of file core_cm85.h.

◆ SCB_CCSIDR_WB_Msk [7/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 948 of file core_cm85.h.

◆ SCB_CCSIDR_RA_Pos [7/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 950 of file core_cm85.h.

◆ SCB_CCSIDR_RA_Msk [7/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 951 of file core_cm85.h.

◆ SCB_CCSIDR_WA_Pos [7/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 953 of file core_cm85.h.

◆ SCB_CCSIDR_WA_Msk [7/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 954 of file core_cm85.h.

◆ SCB_CCSIDR_NUMSETS_Pos [7/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 956 of file core_cm85.h.

◆ SCB_CCSIDR_NUMSETS_Msk [7/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 957 of file core_cm85.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [7/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 959 of file core_cm85.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [7/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 960 of file core_cm85.h.

◆ SCB_CCSIDR_LINESIZE_Pos [7/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 962 of file core_cm85.h.

◆ SCB_CCSIDR_LINESIZE_Msk [7/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 963 of file core_cm85.h.

◆ SCB_CSSELR_LEVEL_Pos [7/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 966 of file core_cm85.h.

◆ SCB_CSSELR_LEVEL_Msk [7/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 967 of file core_cm85.h.

◆ SCB_CSSELR_IND_Pos [7/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 969 of file core_cm85.h.

◆ SCB_CSSELR_IND_Msk [7/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 970 of file core_cm85.h.

◆ SCB_STIR_INTID_Pos [7/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 973 of file core_cm85.h.

◆ SCB_STIR_INTID_Msk [7/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 974 of file core_cm85.h.

◆ SCB_RFSR_V_Pos [3/3]

#define SCB_RFSR_V_Pos   31U

SCB RFSR: V Position

Definition at line 977 of file core_cm85.h.

◆ SCB_RFSR_V_Msk [3/3]

#define SCB_RFSR_V_Msk   (1UL << SCB_RFSR_V_Pos)

SCB RFSR: V Mask

Definition at line 978 of file core_cm85.h.

◆ SCB_RFSR_IS_Pos [3/3]

#define SCB_RFSR_IS_Pos   16U

SCB RFSR: IS Position

Definition at line 980 of file core_cm85.h.

◆ SCB_RFSR_IS_Msk [3/3]

#define SCB_RFSR_IS_Msk   (0x7FFFUL << SCB_RFSR_IS_Pos)

SCB RFSR: IS Mask

Definition at line 981 of file core_cm85.h.

◆ SCB_RFSR_UET_Pos [3/3]

#define SCB_RFSR_UET_Pos   0U

SCB RFSR: UET Position

Definition at line 983 of file core_cm85.h.

◆ SCB_RFSR_UET_Msk [3/3]

#define SCB_RFSR_UET_Msk   (3UL /*<< SCB_RFSR_UET_Pos*/)

SCB RFSR: UET Mask

Definition at line 984 of file core_cm85.h.

◆ SCB_DCISW_WAY_Pos [7/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 987 of file core_cm85.h.

◆ SCB_DCISW_WAY_Msk [7/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 988 of file core_cm85.h.

◆ SCB_DCISW_SET_Pos [7/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 990 of file core_cm85.h.

◆ SCB_DCISW_SET_Msk [7/8]

#define SCB_DCISW_SET_Msk   (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 991 of file core_cm85.h.

◆ SCB_DCCSW_WAY_Pos [7/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 994 of file core_cm85.h.

◆ SCB_DCCSW_WAY_Msk [7/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 995 of file core_cm85.h.

◆ SCB_DCCSW_SET_Pos [7/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 997 of file core_cm85.h.

◆ SCB_DCCSW_SET_Msk [7/8]

#define SCB_DCCSW_SET_Msk   (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 998 of file core_cm85.h.

◆ SCB_DCCISW_WAY_Pos [7/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 1001 of file core_cm85.h.

◆ SCB_DCCISW_WAY_Msk [7/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 1002 of file core_cm85.h.

◆ SCB_DCCISW_SET_Pos [7/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 1004 of file core_cm85.h.

◆ SCB_DCCISW_SET_Msk [7/8]

#define SCB_DCCISW_SET_Msk   (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 1005 of file core_cm85.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [15/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 368 of file core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [15/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 369 of file core_sc000.h.

◆ SCB_CPUID_VARIANT_Pos [15/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 371 of file core_sc000.h.

◆ SCB_CPUID_VARIANT_Msk [15/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 372 of file core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [15/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 374 of file core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [15/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 375 of file core_sc000.h.

◆ SCB_CPUID_PARTNO_Pos [15/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 377 of file core_sc000.h.

◆ SCB_CPUID_PARTNO_Msk [15/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 378 of file core_sc000.h.

◆ SCB_CPUID_REVISION_Pos [15/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 380 of file core_sc000.h.

◆ SCB_CPUID_REVISION_Msk [15/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 381 of file core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Pos [15/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 384 of file core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Msk [15/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 385 of file core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Pos [15/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 387 of file core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Msk [15/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 388 of file core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Pos [15/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 390 of file core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Msk [15/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 391 of file core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Pos [15/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 393 of file core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Msk [15/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 394 of file core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Pos [15/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 396 of file core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Msk [15/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 397 of file core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [15/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 399 of file core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [15/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 400 of file core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Pos [15/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 402 of file core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Msk [15/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 403 of file core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Pos [15/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 405 of file core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Msk [15/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 406 of file core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Pos [15/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 408 of file core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Msk [15/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 409 of file core_sc000.h.

◆ SCB_VTOR_TBLOFF_Pos [10/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 412 of file core_sc000.h.

◆ SCB_VTOR_TBLOFF_Msk [10/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 413 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Pos [15/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 416 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Msk [15/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 417 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [15/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 419 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [15/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 420 of file core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Pos [15/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 422 of file core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Msk [15/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 423 of file core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [15/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 425 of file core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [15/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 426 of file core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [15/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 428 of file core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [15/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 429 of file core_sc000.h.

◆ SCB_SCR_SEVONPEND_Pos [15/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 432 of file core_sc000.h.

◆ SCB_SCR_SEVONPEND_Msk [15/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 433 of file core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Pos [15/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 435 of file core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Msk [15/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 436 of file core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [15/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 438 of file core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [15/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 439 of file core_sc000.h.

◆ SCB_CCR_STKALIGN_Pos [7/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 442 of file core_sc000.h.

◆ SCB_CCR_STKALIGN_Msk [7/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 443 of file core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [15/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 445 of file core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [15/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 446 of file core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [15/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 449 of file core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [15/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 450 of file core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [16/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 407 of file core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [16/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 408 of file core_sc300.h.

◆ SCB_CPUID_VARIANT_Pos [16/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 410 of file core_sc300.h.

◆ SCB_CPUID_VARIANT_Msk [16/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 411 of file core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [16/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 413 of file core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [16/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 414 of file core_sc300.h.

◆ SCB_CPUID_PARTNO_Pos [16/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 416 of file core_sc300.h.

◆ SCB_CPUID_PARTNO_Msk [16/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 417 of file core_sc300.h.

◆ SCB_CPUID_REVISION_Pos [16/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 419 of file core_sc300.h.

◆ SCB_CPUID_REVISION_Msk [16/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 420 of file core_sc300.h.

◆ SCB_ICSR_NMIPENDSET_Pos [16/17]

#define SCB_ICSR_NMIPENDSET_Pos   31U

SCB ICSR: NMIPENDSET Position

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 423 of file core_sc300.h.

◆ SCB_ICSR_NMIPENDSET_Msk [16/17]

#define SCB_ICSR_NMIPENDSET_Msk   (1UL << SCB_ICSR_NMIPENDSET_Pos)

SCB ICSR: NMIPENDSET Mask

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 424 of file core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Pos [16/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 426 of file core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Msk [16/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 427 of file core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Pos [16/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 429 of file core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Msk [16/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 430 of file core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Pos [16/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 432 of file core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Msk [16/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 433 of file core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Pos [16/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 435 of file core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Msk [16/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 436 of file core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [16/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 438 of file core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [16/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 439 of file core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Pos [16/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 441 of file core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Msk [16/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 442 of file core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Pos [16/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 444 of file core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Msk [16/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 445 of file core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Pos [12/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 447 of file core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Msk [12/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 448 of file core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Pos [16/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 450 of file core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Msk [16/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 451 of file core_sc300.h.

◆ SCB_VTOR_TBLBASE_Pos

#define SCB_VTOR_TBLBASE_Pos   29U

SCB VTOR: TBLBASE Position

Definition at line 454 of file core_sc300.h.

◆ SCB_VTOR_TBLBASE_Msk

#define SCB_VTOR_TBLBASE_Msk   (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

Definition at line 455 of file core_sc300.h.

◆ SCB_VTOR_TBLOFF_Pos [11/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 457 of file core_sc300.h.

◆ SCB_VTOR_TBLOFF_Msk [11/12]

#define SCB_VTOR_TBLOFF_Msk   (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 458 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Pos [16/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Msk [16/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [16/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [16/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Pos [16/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Msk [16/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Pos [10/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 470 of file core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Msk [10/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 471 of file core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [16/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 473 of file core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [16/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 474 of file core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [16/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 476 of file core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [16/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 477 of file core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Pos [4/4]

#define SCB_AIRCR_VECTRESET_Pos   0U

SCB AIRCR: VECTRESET Position

Definition at line 479 of file core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Msk [4/4]

#define SCB_AIRCR_VECTRESET_Msk   (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 480 of file core_sc300.h.

◆ SCB_SCR_SEVONPEND_Pos [16/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 483 of file core_sc300.h.

◆ SCB_SCR_SEVONPEND_Msk [16/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 484 of file core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Pos [16/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 486 of file core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Msk [16/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 487 of file core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [16/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 489 of file core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [16/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 490 of file core_sc300.h.

◆ SCB_CCR_STKALIGN_Pos [8/8]

#define SCB_CCR_STKALIGN_Pos   9U

SCB CCR: STKALIGN Position

Definition at line 493 of file core_sc300.h.

◆ SCB_CCR_STKALIGN_Msk [8/8]

#define SCB_CCR_STKALIGN_Msk   (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 494 of file core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Pos [12/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 496 of file core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Msk [12/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 497 of file core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Pos [12/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 499 of file core_sc300.h.

◆ SCB_CCR_DIV_0_TRP_Msk [12/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 500 of file core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [16/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 502 of file core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [16/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 503 of file core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Pos [12/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 505 of file core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Msk [12/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 506 of file core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [4/4]

#define SCB_CCR_NONBASETHRDENA_Pos   0U

SCB CCR: NONBASETHRDENA Position

Definition at line 508 of file core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [4/4]

#define SCB_CCR_NONBASETHRDENA_Msk   (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 509 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [10/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 512 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [10/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 513 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [10/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 515 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [10/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 516 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [10/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 518 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [10/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 519 of file core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [16/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 521 of file core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [16/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 522 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [10/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 524 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [10/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 525 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [10/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 527 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [10/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 528 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [10/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 530 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [10/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 531 of file core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [12/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 533 of file core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [12/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 534 of file core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Pos [12/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 536 of file core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Msk [12/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 537 of file core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Pos [10/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 539 of file core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Msk [10/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 540 of file core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Pos [12/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 542 of file core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Msk [12/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 543 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [10/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 545 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [10/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 546 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [10/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 548 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [10/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 549 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [10/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 551 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [10/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 552 of file core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Pos [10/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 555 of file core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Msk [10/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 556 of file core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [10/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 558 of file core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [10/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 559 of file core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [10/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 561 of file core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [10/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 562 of file core_sc300.h.

◆ SCB_CFSR_MMARVALID_Pos [10/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 565 of file core_sc300.h.

◆ SCB_CFSR_MMARVALID_Msk [10/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 566 of file core_sc300.h.

◆ SCB_CFSR_MSTKERR_Pos [10/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 568 of file core_sc300.h.

◆ SCB_CFSR_MSTKERR_Msk [10/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 569 of file core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Pos [10/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 571 of file core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Msk [10/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 572 of file core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Pos [10/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 574 of file core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Msk [10/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 575 of file core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Pos [10/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 577 of file core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Msk [10/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 578 of file core_sc300.h.

◆ SCB_CFSR_BFARVALID_Pos [10/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 581 of file core_sc300.h.

◆ SCB_CFSR_BFARVALID_Msk [10/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 582 of file core_sc300.h.

◆ SCB_CFSR_STKERR_Pos [10/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 584 of file core_sc300.h.

◆ SCB_CFSR_STKERR_Msk [10/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 585 of file core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Pos [10/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 587 of file core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Msk [10/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 588 of file core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Pos [10/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 590 of file core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Msk [10/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 591 of file core_sc300.h.

◆ SCB_CFSR_PRECISERR_Pos [10/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 593 of file core_sc300.h.

◆ SCB_CFSR_PRECISERR_Msk [10/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 594 of file core_sc300.h.

◆ SCB_CFSR_IBUSERR_Pos [10/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 596 of file core_sc300.h.

◆ SCB_CFSR_IBUSERR_Msk [10/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 597 of file core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Pos [10/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 600 of file core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Msk [10/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 601 of file core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Pos [10/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 603 of file core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Msk [10/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 604 of file core_sc300.h.

◆ SCB_CFSR_NOCP_Pos [10/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 606 of file core_sc300.h.

◆ SCB_CFSR_NOCP_Msk [10/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 607 of file core_sc300.h.

◆ SCB_CFSR_INVPC_Pos [10/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 609 of file core_sc300.h.

◆ SCB_CFSR_INVPC_Msk [10/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 610 of file core_sc300.h.

◆ SCB_CFSR_INVSTATE_Pos [10/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 612 of file core_sc300.h.

◆ SCB_CFSR_INVSTATE_Msk [10/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 613 of file core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [10/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 615 of file core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [10/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 616 of file core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Pos [10/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 619 of file core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Msk [10/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 620 of file core_sc300.h.

◆ SCB_HFSR_FORCED_Pos [10/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 622 of file core_sc300.h.

◆ SCB_HFSR_FORCED_Msk [10/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 623 of file core_sc300.h.

◆ SCB_HFSR_VECTTBL_Pos [10/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 625 of file core_sc300.h.

◆ SCB_HFSR_VECTTBL_Msk [10/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 626 of file core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Pos [10/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 629 of file core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Msk [10/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 630 of file core_sc300.h.

◆ SCB_DFSR_VCATCH_Pos [10/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 632 of file core_sc300.h.

◆ SCB_DFSR_VCATCH_Msk [10/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 633 of file core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Pos [10/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 635 of file core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Msk [10/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 636 of file core_sc300.h.

◆ SCB_DFSR_BKPT_Pos [10/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 638 of file core_sc300.h.

◆ SCB_DFSR_BKPT_Msk [10/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 639 of file core_sc300.h.

◆ SCB_DFSR_HALTED_Pos [10/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 641 of file core_sc300.h.

◆ SCB_DFSR_HALTED_Msk [10/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 642 of file core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [17/17]

#define SCB_CPUID_IMPLEMENTER_Pos   24U

SCB CPUID: IMPLEMENTER Position

Definition at line 568 of file core_starmc1.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [17/17]

#define SCB_CPUID_IMPLEMENTER_Msk   (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 569 of file core_starmc1.h.

◆ SCB_CPUID_VARIANT_Pos [17/17]

#define SCB_CPUID_VARIANT_Pos   20U

SCB CPUID: VARIANT Position

Definition at line 571 of file core_starmc1.h.

◆ SCB_CPUID_VARIANT_Msk [17/17]

#define SCB_CPUID_VARIANT_Msk   (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 572 of file core_starmc1.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [17/17]

#define SCB_CPUID_ARCHITECTURE_Pos   16U

SCB CPUID: ARCHITECTURE Position

Definition at line 574 of file core_starmc1.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [17/17]

#define SCB_CPUID_ARCHITECTURE_Msk   (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 575 of file core_starmc1.h.

◆ SCB_CPUID_PARTNO_Pos [17/17]

#define SCB_CPUID_PARTNO_Pos   4U

SCB CPUID: PARTNO Position

Definition at line 577 of file core_starmc1.h.

◆ SCB_CPUID_PARTNO_Msk [17/17]

#define SCB_CPUID_PARTNO_Msk   (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 578 of file core_starmc1.h.

◆ SCB_CPUID_REVISION_Pos [17/17]

#define SCB_CPUID_REVISION_Pos   0U

SCB CPUID: REVISION Position

Definition at line 580 of file core_starmc1.h.

◆ SCB_CPUID_REVISION_Msk [17/17]

#define SCB_CPUID_REVISION_Msk   (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 581 of file core_starmc1.h.

◆ SCB_ICSR_PENDNMISET_Pos [9/9]

#define SCB_ICSR_PENDNMISET_Pos   31U

SCB ICSR: PENDNMISET Position

Definition at line 584 of file core_starmc1.h.

◆ SCB_ICSR_PENDNMISET_Msk [9/9]

#define SCB_ICSR_PENDNMISET_Msk   (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 585 of file core_starmc1.h.

◆ SCB_ICSR_NMIPENDSET_Pos [17/17]

#define SCB_ICSR_NMIPENDSET_Pos   SCB_ICSR_PENDNMISET_Pos

SCB ICSR: NMIPENDSET Position, backward compatibility

Definition at line 587 of file core_starmc1.h.

◆ SCB_ICSR_NMIPENDSET_Msk [17/17]

#define SCB_ICSR_NMIPENDSET_Msk   SCB_ICSR_PENDNMISET_Msk

SCB ICSR: NMIPENDSET Mask, backward compatibility

Definition at line 588 of file core_starmc1.h.

◆ SCB_ICSR_PENDNMICLR_Pos [9/9]

#define SCB_ICSR_PENDNMICLR_Pos   30U

SCB ICSR: PENDNMICLR Position

Definition at line 590 of file core_starmc1.h.

◆ SCB_ICSR_PENDNMICLR_Msk [9/9]

#define SCB_ICSR_PENDNMICLR_Msk   (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 591 of file core_starmc1.h.

◆ SCB_ICSR_PENDSVSET_Pos [17/17]

#define SCB_ICSR_PENDSVSET_Pos   28U

SCB ICSR: PENDSVSET Position

Definition at line 593 of file core_starmc1.h.

◆ SCB_ICSR_PENDSVSET_Msk [17/17]

#define SCB_ICSR_PENDSVSET_Msk   (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 594 of file core_starmc1.h.

◆ SCB_ICSR_PENDSVCLR_Pos [17/17]

#define SCB_ICSR_PENDSVCLR_Pos   27U

SCB ICSR: PENDSVCLR Position

Definition at line 596 of file core_starmc1.h.

◆ SCB_ICSR_PENDSVCLR_Msk [17/17]

#define SCB_ICSR_PENDSVCLR_Msk   (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 597 of file core_starmc1.h.

◆ SCB_ICSR_PENDSTSET_Pos [17/17]

#define SCB_ICSR_PENDSTSET_Pos   26U

SCB ICSR: PENDSTSET Position

Definition at line 599 of file core_starmc1.h.

◆ SCB_ICSR_PENDSTSET_Msk [17/17]

#define SCB_ICSR_PENDSTSET_Msk   (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 600 of file core_starmc1.h.

◆ SCB_ICSR_PENDSTCLR_Pos [17/17]

#define SCB_ICSR_PENDSTCLR_Pos   25U

SCB ICSR: PENDSTCLR Position

Definition at line 602 of file core_starmc1.h.

◆ SCB_ICSR_PENDSTCLR_Msk [17/17]

#define SCB_ICSR_PENDSTCLR_Msk   (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 603 of file core_starmc1.h.

◆ SCB_ICSR_STTNS_Pos [9/9]

#define SCB_ICSR_STTNS_Pos   24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 605 of file core_starmc1.h.

◆ SCB_ICSR_STTNS_Msk [9/9]

#define SCB_ICSR_STTNS_Msk   (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 606 of file core_starmc1.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [17/17]

#define SCB_ICSR_ISRPREEMPT_Pos   23U

SCB ICSR: ISRPREEMPT Position

Definition at line 608 of file core_starmc1.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [17/17]

#define SCB_ICSR_ISRPREEMPT_Msk   (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 609 of file core_starmc1.h.

◆ SCB_ICSR_ISRPENDING_Pos [17/17]

#define SCB_ICSR_ISRPENDING_Pos   22U

SCB ICSR: ISRPENDING Position

Definition at line 611 of file core_starmc1.h.

◆ SCB_ICSR_ISRPENDING_Msk [17/17]

#define SCB_ICSR_ISRPENDING_Msk   (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 612 of file core_starmc1.h.

◆ SCB_ICSR_VECTPENDING_Pos [17/17]

#define SCB_ICSR_VECTPENDING_Pos   12U

SCB ICSR: VECTPENDING Position

Definition at line 614 of file core_starmc1.h.

◆ SCB_ICSR_VECTPENDING_Msk [17/17]

#define SCB_ICSR_VECTPENDING_Msk   (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 615 of file core_starmc1.h.

◆ SCB_ICSR_RETTOBASE_Pos [13/13]

#define SCB_ICSR_RETTOBASE_Pos   11U

SCB ICSR: RETTOBASE Position

Definition at line 617 of file core_starmc1.h.

◆ SCB_ICSR_RETTOBASE_Msk [13/13]

#define SCB_ICSR_RETTOBASE_Msk   (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 618 of file core_starmc1.h.

◆ SCB_ICSR_VECTACTIVE_Pos [17/17]

#define SCB_ICSR_VECTACTIVE_Pos   0U

SCB ICSR: VECTACTIVE Position

Definition at line 620 of file core_starmc1.h.

◆ SCB_ICSR_VECTACTIVE_Msk [17/17]

#define SCB_ICSR_VECTACTIVE_Msk   (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 621 of file core_starmc1.h.

◆ SCB_VTOR_TBLOFF_Pos [12/12]

#define SCB_VTOR_TBLOFF_Pos   7U

SCB VTOR: TBLOFF Position

Definition at line 624 of file core_starmc1.h.

◆ SCB_VTOR_TBLOFF_Msk [12/12]

#define SCB_VTOR_TBLOFF_Msk   (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 625 of file core_starmc1.h.

◆ SCB_AIRCR_VECTKEY_Pos [17/17]

#define SCB_AIRCR_VECTKEY_Pos   16U

SCB AIRCR: VECTKEY Position

Definition at line 628 of file core_starmc1.h.

◆ SCB_AIRCR_VECTKEY_Msk [17/17]

#define SCB_AIRCR_VECTKEY_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 629 of file core_starmc1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [17/17]

#define SCB_AIRCR_VECTKEYSTAT_Pos   16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 631 of file core_starmc1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [17/17]

#define SCB_AIRCR_VECTKEYSTAT_Msk   (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 632 of file core_starmc1.h.

◆ SCB_AIRCR_ENDIANESS_Pos [17/17]

#define SCB_AIRCR_ENDIANESS_Pos   15U

SCB AIRCR: ENDIANESS Position

Definition at line 634 of file core_starmc1.h.

◆ SCB_AIRCR_ENDIANESS_Msk [17/17]

#define SCB_AIRCR_ENDIANESS_Msk   (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 635 of file core_starmc1.h.

◆ SCB_AIRCR_PRIS_Pos [9/9]

#define SCB_AIRCR_PRIS_Pos   14U

SCB AIRCR: PRIS Position

Definition at line 637 of file core_starmc1.h.

◆ SCB_AIRCR_PRIS_Msk [9/9]

#define SCB_AIRCR_PRIS_Msk   (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 638 of file core_starmc1.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [9/9]

#define SCB_AIRCR_BFHFNMINS_Pos   13U

SCB AIRCR: BFHFNMINS Position

Definition at line 640 of file core_starmc1.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [9/9]

#define SCB_AIRCR_BFHFNMINS_Msk   (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 641 of file core_starmc1.h.

◆ SCB_AIRCR_PRIGROUP_Pos [11/11]

#define SCB_AIRCR_PRIGROUP_Pos   8U

SCB AIRCR: PRIGROUP Position

Definition at line 643 of file core_starmc1.h.

◆ SCB_AIRCR_PRIGROUP_Msk [11/11]

#define SCB_AIRCR_PRIGROUP_Msk   (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 644 of file core_starmc1.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [9/9]

#define SCB_AIRCR_SYSRESETREQS_Pos   3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 646 of file core_starmc1.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [9/9]

#define SCB_AIRCR_SYSRESETREQS_Msk   (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 647 of file core_starmc1.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [17/17]

#define SCB_AIRCR_SYSRESETREQ_Pos   2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 649 of file core_starmc1.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [17/17]

#define SCB_AIRCR_SYSRESETREQ_Msk   (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 650 of file core_starmc1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [17/17]

#define SCB_AIRCR_VECTCLRACTIVE_Pos   1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 652 of file core_starmc1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [17/17]

#define SCB_AIRCR_VECTCLRACTIVE_Msk   (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 653 of file core_starmc1.h.

◆ SCB_SCR_SEVONPEND_Pos [17/17]

#define SCB_SCR_SEVONPEND_Pos   4U

SCB SCR: SEVONPEND Position

Definition at line 656 of file core_starmc1.h.

◆ SCB_SCR_SEVONPEND_Msk [17/17]

#define SCB_SCR_SEVONPEND_Msk   (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 657 of file core_starmc1.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [9/9]

#define SCB_SCR_SLEEPDEEPS_Pos   3U

SCB SCR: SLEEPDEEPS Position

Definition at line 659 of file core_starmc1.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [9/9]

#define SCB_SCR_SLEEPDEEPS_Msk   (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 660 of file core_starmc1.h.

◆ SCB_SCR_SLEEPDEEP_Pos [17/17]

#define SCB_SCR_SLEEPDEEP_Pos   2U

SCB SCR: SLEEPDEEP Position

Definition at line 662 of file core_starmc1.h.

◆ SCB_SCR_SLEEPDEEP_Msk [17/17]

#define SCB_SCR_SLEEPDEEP_Msk   (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 663 of file core_starmc1.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [17/17]

#define SCB_SCR_SLEEPONEXIT_Pos   1U

SCB SCR: SLEEPONEXIT Position

Definition at line 665 of file core_starmc1.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [17/17]

#define SCB_SCR_SLEEPONEXIT_Msk   (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 666 of file core_starmc1.h.

◆ SCB_CCR_BP_Pos [10/10]

#define SCB_CCR_BP_Pos   18U

SCB CCR: BP Position

Definition at line 669 of file core_starmc1.h.

◆ SCB_CCR_BP_Msk [10/10]

#define SCB_CCR_BP_Msk   (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

Definition at line 670 of file core_starmc1.h.

◆ SCB_CCR_IC_Pos [10/10]

#define SCB_CCR_IC_Pos   17U

SCB CCR: IC Position

Definition at line 672 of file core_starmc1.h.

◆ SCB_CCR_IC_Msk [10/10]

#define SCB_CCR_IC_Msk   (1UL << SCB_CCR_IC_Pos)

SCB CCR: IC Mask

Definition at line 673 of file core_starmc1.h.

◆ SCB_CCR_DC_Pos [10/10]

#define SCB_CCR_DC_Pos   16U

SCB CCR: DC Position

Definition at line 675 of file core_starmc1.h.

◆ SCB_CCR_DC_Msk [10/10]

#define SCB_CCR_DC_Msk   (1UL << SCB_CCR_DC_Pos)

SCB CCR: DC Mask

Definition at line 676 of file core_starmc1.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [9/9]

#define SCB_CCR_STKOFHFNMIGN_Pos   10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 678 of file core_starmc1.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [9/9]

#define SCB_CCR_STKOFHFNMIGN_Msk   (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 679 of file core_starmc1.h.

◆ SCB_CCR_BFHFNMIGN_Pos [13/13]

#define SCB_CCR_BFHFNMIGN_Pos   8U

SCB CCR: BFHFNMIGN Position

Definition at line 681 of file core_starmc1.h.

◆ SCB_CCR_BFHFNMIGN_Msk [13/13]

#define SCB_CCR_BFHFNMIGN_Msk   (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 682 of file core_starmc1.h.

◆ SCB_CCR_DIV_0_TRP_Pos [13/13]

#define SCB_CCR_DIV_0_TRP_Pos   4U

SCB CCR: DIV_0_TRP Position

Definition at line 684 of file core_starmc1.h.

◆ SCB_CCR_DIV_0_TRP_Msk [13/13]

#define SCB_CCR_DIV_0_TRP_Msk   (1UL << SCB_CCR_DIV_0_TRP_Pos)

SCB CCR: DIV_0_TRP Mask

Definition at line 685 of file core_starmc1.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [17/17]

#define SCB_CCR_UNALIGN_TRP_Pos   3U

SCB CCR: UNALIGN_TRP Position

Definition at line 687 of file core_starmc1.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [17/17]

#define SCB_CCR_UNALIGN_TRP_Msk   (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 688 of file core_starmc1.h.

◆ SCB_CCR_USERSETMPEND_Pos [13/13]

#define SCB_CCR_USERSETMPEND_Pos   1U

SCB CCR: USERSETMPEND Position

Definition at line 690 of file core_starmc1.h.

◆ SCB_CCR_USERSETMPEND_Msk [13/13]

#define SCB_CCR_USERSETMPEND_Msk   (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 691 of file core_starmc1.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [9/9]

#define SCB_SHCSR_HARDFAULTPENDED_Pos   21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 694 of file core_starmc1.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [9/9]

#define SCB_SHCSR_HARDFAULTPENDED_Msk   (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 695 of file core_starmc1.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [7/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos   20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 697 of file core_starmc1.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [7/7]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk   (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 698 of file core_starmc1.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [7/7]

#define SCB_SHCSR_SECUREFAULTENA_Pos   19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 700 of file core_starmc1.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [7/7]

#define SCB_SHCSR_SECUREFAULTENA_Msk   (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 701 of file core_starmc1.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [11/11]

#define SCB_SHCSR_USGFAULTENA_Pos   18U

SCB SHCSR: USGFAULTENA Position

Definition at line 703 of file core_starmc1.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [11/11]

#define SCB_SHCSR_USGFAULTENA_Msk   (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 704 of file core_starmc1.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [11/11]

#define SCB_SHCSR_BUSFAULTENA_Pos   17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 706 of file core_starmc1.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [11/11]

#define SCB_SHCSR_BUSFAULTENA_Msk   (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 707 of file core_starmc1.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [11/11]

#define SCB_SHCSR_MEMFAULTENA_Pos   16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 709 of file core_starmc1.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [11/11]

#define SCB_SHCSR_MEMFAULTENA_Msk   (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 710 of file core_starmc1.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [17/17]

#define SCB_SHCSR_SVCALLPENDED_Pos   15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 712 of file core_starmc1.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [17/17]

#define SCB_SHCSR_SVCALLPENDED_Msk   (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 713 of file core_starmc1.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [11/11]

#define SCB_SHCSR_BUSFAULTPENDED_Pos   14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 715 of file core_starmc1.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [11/11]

#define SCB_SHCSR_BUSFAULTPENDED_Msk   (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 716 of file core_starmc1.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [11/11]

#define SCB_SHCSR_MEMFAULTPENDED_Pos   13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 718 of file core_starmc1.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [11/11]

#define SCB_SHCSR_MEMFAULTPENDED_Msk   (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 719 of file core_starmc1.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [11/11]

#define SCB_SHCSR_USGFAULTPENDED_Pos   12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 721 of file core_starmc1.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [11/11]

#define SCB_SHCSR_USGFAULTPENDED_Msk   (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 722 of file core_starmc1.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [13/13]

#define SCB_SHCSR_SYSTICKACT_Pos   11U

SCB SHCSR: SYSTICKACT Position

Definition at line 724 of file core_starmc1.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [13/13]

#define SCB_SHCSR_SYSTICKACT_Msk   (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 725 of file core_starmc1.h.

◆ SCB_SHCSR_PENDSVACT_Pos [13/13]

#define SCB_SHCSR_PENDSVACT_Pos   10U

SCB SHCSR: PENDSVACT Position

Definition at line 727 of file core_starmc1.h.

◆ SCB_SHCSR_PENDSVACT_Msk [13/13]

#define SCB_SHCSR_PENDSVACT_Msk   (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 728 of file core_starmc1.h.

◆ SCB_SHCSR_MONITORACT_Pos [11/11]

#define SCB_SHCSR_MONITORACT_Pos   8U

SCB SHCSR: MONITORACT Position

Definition at line 730 of file core_starmc1.h.

◆ SCB_SHCSR_MONITORACT_Msk [11/11]

#define SCB_SHCSR_MONITORACT_Msk   (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 731 of file core_starmc1.h.

◆ SCB_SHCSR_SVCALLACT_Pos [13/13]

#define SCB_SHCSR_SVCALLACT_Pos   7U

SCB SHCSR: SVCALLACT Position

Definition at line 733 of file core_starmc1.h.

◆ SCB_SHCSR_SVCALLACT_Msk [13/13]

#define SCB_SHCSR_SVCALLACT_Msk   (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 734 of file core_starmc1.h.

◆ SCB_SHCSR_NMIACT_Pos [9/9]

#define SCB_SHCSR_NMIACT_Pos   5U

SCB SHCSR: NMIACT Position

Definition at line 736 of file core_starmc1.h.

◆ SCB_SHCSR_NMIACT_Msk [9/9]

#define SCB_SHCSR_NMIACT_Msk   (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 737 of file core_starmc1.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [7/7]

#define SCB_SHCSR_SECUREFAULTACT_Pos   4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 739 of file core_starmc1.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [7/7]

#define SCB_SHCSR_SECUREFAULTACT_Msk   (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 740 of file core_starmc1.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [11/11]

#define SCB_SHCSR_USGFAULTACT_Pos   3U

SCB SHCSR: USGFAULTACT Position

Definition at line 742 of file core_starmc1.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [11/11]

#define SCB_SHCSR_USGFAULTACT_Msk   (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 743 of file core_starmc1.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [9/9]

#define SCB_SHCSR_HARDFAULTACT_Pos   2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 745 of file core_starmc1.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [9/9]

#define SCB_SHCSR_HARDFAULTACT_Msk   (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 746 of file core_starmc1.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [11/11]

#define SCB_SHCSR_BUSFAULTACT_Pos   1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 748 of file core_starmc1.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [11/11]

#define SCB_SHCSR_BUSFAULTACT_Msk   (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 749 of file core_starmc1.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [11/11]

#define SCB_SHCSR_MEMFAULTACT_Pos   0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 751 of file core_starmc1.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [11/11]

#define SCB_SHCSR_MEMFAULTACT_Msk   (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 752 of file core_starmc1.h.

◆ SCB_CFSR_USGFAULTSR_Pos [11/11]

#define SCB_CFSR_USGFAULTSR_Pos   16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 755 of file core_starmc1.h.

◆ SCB_CFSR_USGFAULTSR_Msk [11/11]

#define SCB_CFSR_USGFAULTSR_Msk   (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 756 of file core_starmc1.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [11/11]

#define SCB_CFSR_BUSFAULTSR_Pos   8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 758 of file core_starmc1.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [11/11]

#define SCB_CFSR_BUSFAULTSR_Msk   (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 759 of file core_starmc1.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [11/11]

#define SCB_CFSR_MEMFAULTSR_Pos   0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 761 of file core_starmc1.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [11/11]

#define SCB_CFSR_MEMFAULTSR_Msk   (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 762 of file core_starmc1.h.

◆ SCB_CFSR_MMARVALID_Pos [11/11]

#define SCB_CFSR_MMARVALID_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 765 of file core_starmc1.h.

◆ SCB_CFSR_MMARVALID_Msk [11/11]

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 766 of file core_starmc1.h.

◆ SCB_CFSR_MLSPERR_Pos [9/9]

#define SCB_CFSR_MLSPERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 768 of file core_starmc1.h.

◆ SCB_CFSR_MLSPERR_Msk [9/9]

#define SCB_CFSR_MLSPERR_Msk   (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 769 of file core_starmc1.h.

◆ SCB_CFSR_MSTKERR_Pos [11/11]

#define SCB_CFSR_MSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 771 of file core_starmc1.h.

◆ SCB_CFSR_MSTKERR_Msk [11/11]

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 772 of file core_starmc1.h.

◆ SCB_CFSR_MUNSTKERR_Pos [11/11]

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 774 of file core_starmc1.h.

◆ SCB_CFSR_MUNSTKERR_Msk [11/11]

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 775 of file core_starmc1.h.

◆ SCB_CFSR_DACCVIOL_Pos [11/11]

#define SCB_CFSR_DACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 777 of file core_starmc1.h.

◆ SCB_CFSR_DACCVIOL_Msk [11/11]

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 778 of file core_starmc1.h.

◆ SCB_CFSR_IACCVIOL_Pos [11/11]

#define SCB_CFSR_IACCVIOL_Pos   (SCB_CFSR_MEMFAULTSR_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 780 of file core_starmc1.h.

◆ SCB_CFSR_IACCVIOL_Msk [11/11]

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 781 of file core_starmc1.h.

◆ SCB_CFSR_BFARVALID_Pos [11/11]

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 784 of file core_starmc1.h.

◆ SCB_CFSR_BFARVALID_Msk [11/11]

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 785 of file core_starmc1.h.

◆ SCB_CFSR_LSPERR_Pos [9/9]

#define SCB_CFSR_LSPERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 787 of file core_starmc1.h.

◆ SCB_CFSR_LSPERR_Msk [9/9]

#define SCB_CFSR_LSPERR_Msk   (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 788 of file core_starmc1.h.

◆ SCB_CFSR_STKERR_Pos [11/11]

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 790 of file core_starmc1.h.

◆ SCB_CFSR_STKERR_Msk [11/11]

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 791 of file core_starmc1.h.

◆ SCB_CFSR_UNSTKERR_Pos [11/11]

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 793 of file core_starmc1.h.

◆ SCB_CFSR_UNSTKERR_Msk [11/11]

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 794 of file core_starmc1.h.

◆ SCB_CFSR_IMPRECISERR_Pos [11/11]

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 796 of file core_starmc1.h.

◆ SCB_CFSR_IMPRECISERR_Msk [11/11]

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 797 of file core_starmc1.h.

◆ SCB_CFSR_PRECISERR_Pos [11/11]

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 799 of file core_starmc1.h.

◆ SCB_CFSR_PRECISERR_Msk [11/11]

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 800 of file core_starmc1.h.

◆ SCB_CFSR_IBUSERR_Pos [11/11]

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 802 of file core_starmc1.h.

◆ SCB_CFSR_IBUSERR_Msk [11/11]

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 803 of file core_starmc1.h.

◆ SCB_CFSR_DIVBYZERO_Pos [11/11]

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 806 of file core_starmc1.h.

◆ SCB_CFSR_DIVBYZERO_Msk [11/11]

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 807 of file core_starmc1.h.

◆ SCB_CFSR_UNALIGNED_Pos [11/11]

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 809 of file core_starmc1.h.

◆ SCB_CFSR_UNALIGNED_Msk [11/11]

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 810 of file core_starmc1.h.

◆ SCB_CFSR_STKOF_Pos [7/7]

#define SCB_CFSR_STKOF_Pos   (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 812 of file core_starmc1.h.

◆ SCB_CFSR_STKOF_Msk [7/7]

#define SCB_CFSR_STKOF_Msk   (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 813 of file core_starmc1.h.

◆ SCB_CFSR_NOCP_Pos [11/11]

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 815 of file core_starmc1.h.

◆ SCB_CFSR_NOCP_Msk [11/11]

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 816 of file core_starmc1.h.

◆ SCB_CFSR_INVPC_Pos [11/11]

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 818 of file core_starmc1.h.

◆ SCB_CFSR_INVPC_Msk [11/11]

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 819 of file core_starmc1.h.

◆ SCB_CFSR_INVSTATE_Pos [11/11]

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 821 of file core_starmc1.h.

◆ SCB_CFSR_INVSTATE_Msk [11/11]

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 822 of file core_starmc1.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [11/11]

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 824 of file core_starmc1.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [11/11]

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 825 of file core_starmc1.h.

◆ SCB_HFSR_DEBUGEVT_Pos [11/11]

#define SCB_HFSR_DEBUGEVT_Pos   31U

SCB HFSR: DEBUGEVT Position

Definition at line 828 of file core_starmc1.h.

◆ SCB_HFSR_DEBUGEVT_Msk [11/11]

#define SCB_HFSR_DEBUGEVT_Msk   (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 829 of file core_starmc1.h.

◆ SCB_HFSR_FORCED_Pos [11/11]

#define SCB_HFSR_FORCED_Pos   30U

SCB HFSR: FORCED Position

Definition at line 831 of file core_starmc1.h.

◆ SCB_HFSR_FORCED_Msk [11/11]

#define SCB_HFSR_FORCED_Msk   (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 832 of file core_starmc1.h.

◆ SCB_HFSR_VECTTBL_Pos [11/11]

#define SCB_HFSR_VECTTBL_Pos   1U

SCB HFSR: VECTTBL Position

Definition at line 834 of file core_starmc1.h.

◆ SCB_HFSR_VECTTBL_Msk [11/11]

#define SCB_HFSR_VECTTBL_Msk   (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 835 of file core_starmc1.h.

◆ SCB_DFSR_EXTERNAL_Pos [11/11]

#define SCB_DFSR_EXTERNAL_Pos   4U

SCB DFSR: EXTERNAL Position

Definition at line 838 of file core_starmc1.h.

◆ SCB_DFSR_EXTERNAL_Msk [11/11]

#define SCB_DFSR_EXTERNAL_Msk   (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 839 of file core_starmc1.h.

◆ SCB_DFSR_VCATCH_Pos [11/11]

#define SCB_DFSR_VCATCH_Pos   3U

SCB DFSR: VCATCH Position

Definition at line 841 of file core_starmc1.h.

◆ SCB_DFSR_VCATCH_Msk [11/11]

#define SCB_DFSR_VCATCH_Msk   (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 842 of file core_starmc1.h.

◆ SCB_DFSR_DWTTRAP_Pos [11/11]

#define SCB_DFSR_DWTTRAP_Pos   2U

SCB DFSR: DWTTRAP Position

Definition at line 844 of file core_starmc1.h.

◆ SCB_DFSR_DWTTRAP_Msk [11/11]

#define SCB_DFSR_DWTTRAP_Msk   (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 845 of file core_starmc1.h.

◆ SCB_DFSR_BKPT_Pos [11/11]

#define SCB_DFSR_BKPT_Pos   1U

SCB DFSR: BKPT Position

Definition at line 847 of file core_starmc1.h.

◆ SCB_DFSR_BKPT_Msk [11/11]

#define SCB_DFSR_BKPT_Msk   (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 848 of file core_starmc1.h.

◆ SCB_DFSR_HALTED_Pos [11/11]

#define SCB_DFSR_HALTED_Pos   0U

SCB DFSR: HALTED Position

Definition at line 850 of file core_starmc1.h.

◆ SCB_DFSR_HALTED_Msk [11/11]

#define SCB_DFSR_HALTED_Msk   (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 851 of file core_starmc1.h.

◆ SCB_NSACR_CP11_Pos [7/7]

#define SCB_NSACR_CP11_Pos   11U

SCB NSACR: CP11 Position

Definition at line 854 of file core_starmc1.h.

◆ SCB_NSACR_CP11_Msk [7/7]

#define SCB_NSACR_CP11_Msk   (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 855 of file core_starmc1.h.

◆ SCB_NSACR_CP10_Pos [7/7]

#define SCB_NSACR_CP10_Pos   10U

SCB NSACR: CP10 Position

Definition at line 857 of file core_starmc1.h.

◆ SCB_NSACR_CP10_Msk [7/7]

#define SCB_NSACR_CP10_Msk   (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 858 of file core_starmc1.h.

◆ SCB_NSACR_CPn_Pos [4/4]

#define SCB_NSACR_CPn_Pos   0U

SCB NSACR: CPn Position

Definition at line 860 of file core_starmc1.h.

◆ SCB_NSACR_CPn_Msk [4/4]

#define SCB_NSACR_CPn_Msk   (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 861 of file core_starmc1.h.

◆ SCB_CLIDR_LOUU_Pos [8/8]

#define SCB_CLIDR_LOUU_Pos   27U

SCB CLIDR: LoUU Position

Definition at line 864 of file core_starmc1.h.

◆ SCB_CLIDR_LOUU_Msk [8/8]

#define SCB_CLIDR_LOUU_Msk   (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 865 of file core_starmc1.h.

◆ SCB_CLIDR_LOC_Pos [8/8]

#define SCB_CLIDR_LOC_Pos   24U

SCB CLIDR: LoC Position

Definition at line 867 of file core_starmc1.h.

◆ SCB_CLIDR_LOC_Msk [8/8]

#define SCB_CLIDR_LOC_Msk   (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 868 of file core_starmc1.h.

◆ SCB_CLIDR_IC_Pos

#define SCB_CLIDR_IC_Pos   0U

SCB CLIDR: IC Position

Definition at line 870 of file core_starmc1.h.

◆ SCB_CLIDR_IC_Msk

#define SCB_CLIDR_IC_Msk   (1UL << SCB_CLIDR_IC_Pos)

SCB CLIDR: IC Mask

Definition at line 871 of file core_starmc1.h.

◆ SCB_CLIDR_DC_Pos

#define SCB_CLIDR_DC_Pos   1U

SCB CLIDR: DC Position

Definition at line 873 of file core_starmc1.h.

◆ SCB_CLIDR_DC_Msk

#define SCB_CLIDR_DC_Msk   (1UL << SCB_CLIDR_DC_Pos)

SCB CLIDR: DC Mask

Definition at line 874 of file core_starmc1.h.

◆ SCB_CTR_FORMAT_Pos [8/8]

#define SCB_CTR_FORMAT_Pos   29U

SCB CTR: Format Position

Definition at line 879 of file core_starmc1.h.

◆ SCB_CTR_FORMAT_Msk [8/8]

#define SCB_CTR_FORMAT_Msk   (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 880 of file core_starmc1.h.

◆ SCB_CTR_CWG_Pos [8/8]

#define SCB_CTR_CWG_Pos   24U

SCB CTR: CWG Position

Definition at line 882 of file core_starmc1.h.

◆ SCB_CTR_CWG_Msk [8/8]

#define SCB_CTR_CWG_Msk   (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 883 of file core_starmc1.h.

◆ SCB_CTR_ERG_Pos [8/8]

#define SCB_CTR_ERG_Pos   20U

SCB CTR: ERG Position

Definition at line 885 of file core_starmc1.h.

◆ SCB_CTR_ERG_Msk [8/8]

#define SCB_CTR_ERG_Msk   (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 886 of file core_starmc1.h.

◆ SCB_CTR_DMINLINE_Pos [8/8]

#define SCB_CTR_DMINLINE_Pos   16U

SCB CTR: DminLine Position

Definition at line 888 of file core_starmc1.h.

◆ SCB_CTR_DMINLINE_Msk [8/8]

#define SCB_CTR_DMINLINE_Msk   (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 889 of file core_starmc1.h.

◆ SCB_CTR_IMINLINE_Pos [8/8]

#define SCB_CTR_IMINLINE_Pos   0U

SCB CTR: ImInLine Position

Definition at line 891 of file core_starmc1.h.

◆ SCB_CTR_IMINLINE_Msk [8/8]

#define SCB_CTR_IMINLINE_Msk   (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 892 of file core_starmc1.h.

◆ SCB_CCSIDR_WT_Pos [8/8]

#define SCB_CCSIDR_WT_Pos   31U

SCB CCSIDR: WT Position

Definition at line 895 of file core_starmc1.h.

◆ SCB_CCSIDR_WT_Msk [8/8]

#define SCB_CCSIDR_WT_Msk   (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 896 of file core_starmc1.h.

◆ SCB_CCSIDR_WB_Pos [8/8]

#define SCB_CCSIDR_WB_Pos   30U

SCB CCSIDR: WB Position

Definition at line 898 of file core_starmc1.h.

◆ SCB_CCSIDR_WB_Msk [8/8]

#define SCB_CCSIDR_WB_Msk   (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 899 of file core_starmc1.h.

◆ SCB_CCSIDR_RA_Pos [8/8]

#define SCB_CCSIDR_RA_Pos   29U

SCB CCSIDR: RA Position

Definition at line 901 of file core_starmc1.h.

◆ SCB_CCSIDR_RA_Msk [8/8]

#define SCB_CCSIDR_RA_Msk   (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 902 of file core_starmc1.h.

◆ SCB_CCSIDR_WA_Pos [8/8]

#define SCB_CCSIDR_WA_Pos   28U

SCB CCSIDR: WA Position

Definition at line 904 of file core_starmc1.h.

◆ SCB_CCSIDR_WA_Msk [8/8]

#define SCB_CCSIDR_WA_Msk   (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 905 of file core_starmc1.h.

◆ SCB_CCSIDR_NUMSETS_Pos [8/8]

#define SCB_CCSIDR_NUMSETS_Pos   13U

SCB CCSIDR: NumSets Position

Definition at line 907 of file core_starmc1.h.

◆ SCB_CCSIDR_NUMSETS_Msk [8/8]

#define SCB_CCSIDR_NUMSETS_Msk   (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 908 of file core_starmc1.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [8/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos   3U

SCB CCSIDR: Associativity Position

Definition at line 910 of file core_starmc1.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [8/8]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk   (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 911 of file core_starmc1.h.

◆ SCB_CCSIDR_LINESIZE_Pos [8/8]

#define SCB_CCSIDR_LINESIZE_Pos   0U

SCB CCSIDR: LineSize Position

Definition at line 913 of file core_starmc1.h.

◆ SCB_CCSIDR_LINESIZE_Msk [8/8]

#define SCB_CCSIDR_LINESIZE_Msk   (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 914 of file core_starmc1.h.

◆ SCB_CSSELR_LEVEL_Pos [8/8]

#define SCB_CSSELR_LEVEL_Pos   1U

SCB CSSELR: Level Position

Definition at line 917 of file core_starmc1.h.

◆ SCB_CSSELR_LEVEL_Msk [8/8]

#define SCB_CSSELR_LEVEL_Msk   (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 918 of file core_starmc1.h.

◆ SCB_CSSELR_IND_Pos [8/8]

#define SCB_CSSELR_IND_Pos   0U

SCB CSSELR: InD Position

Definition at line 920 of file core_starmc1.h.

◆ SCB_CSSELR_IND_Msk [8/8]

#define SCB_CSSELR_IND_Msk   (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 921 of file core_starmc1.h.

◆ SCB_STIR_INTID_Pos [8/8]

#define SCB_STIR_INTID_Pos   0U

SCB STIR: INTID Position

Definition at line 924 of file core_starmc1.h.

◆ SCB_STIR_INTID_Msk [8/8]

#define SCB_STIR_INTID_Msk   (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 925 of file core_starmc1.h.

◆ SCB_DCISW_LEVEL_Pos

#define SCB_DCISW_LEVEL_Pos   1U

SCB DCISW: Level Position

Definition at line 928 of file core_starmc1.h.

◆ SCB_DCISW_LEVEL_Msk

#define SCB_DCISW_LEVEL_Msk   (7UL << SCB_DCISW_LEVEL_Pos)

SCB DCISW: Level Mask

Definition at line 929 of file core_starmc1.h.

◆ SCB_DCISW_WAY_Pos [8/8]

#define SCB_DCISW_WAY_Pos   30U

SCB DCISW: Way Position

Definition at line 931 of file core_starmc1.h.

◆ SCB_DCISW_WAY_Msk [8/8]

#define SCB_DCISW_WAY_Msk   (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 932 of file core_starmc1.h.

◆ SCB_DCISW_SET_Pos [8/8]

#define SCB_DCISW_SET_Pos   5U

SCB DCISW: Set Position

Definition at line 934 of file core_starmc1.h.

◆ SCB_DCISW_SET_Msk [8/8]

#define SCB_DCISW_SET_Msk   (0xFFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 935 of file core_starmc1.h.

◆ SCB_DCCSW_LEVEL_Pos

#define SCB_DCCSW_LEVEL_Pos   1U

SCB DCCSW: Level Position

Definition at line 938 of file core_starmc1.h.

◆ SCB_DCCSW_LEVEL_Msk

#define SCB_DCCSW_LEVEL_Msk   (7UL << SCB_DCCSW_LEVEL_Pos)

SCB DCCSW: Level Mask

Definition at line 939 of file core_starmc1.h.

◆ SCB_DCCSW_WAY_Pos [8/8]

#define SCB_DCCSW_WAY_Pos   30U

SCB DCCSW: Way Position

Definition at line 941 of file core_starmc1.h.

◆ SCB_DCCSW_WAY_Msk [8/8]

#define SCB_DCCSW_WAY_Msk   (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 942 of file core_starmc1.h.

◆ SCB_DCCSW_SET_Pos [8/8]

#define SCB_DCCSW_SET_Pos   5U

SCB DCCSW: Set Position

Definition at line 944 of file core_starmc1.h.

◆ SCB_DCCSW_SET_Msk [8/8]

#define SCB_DCCSW_SET_Msk   (0xFFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 945 of file core_starmc1.h.

◆ SCB_DCCISW_LEVEL_Pos

#define SCB_DCCISW_LEVEL_Pos   1U

SCB DCCISW: Level Position

Definition at line 948 of file core_starmc1.h.

◆ SCB_DCCISW_LEVEL_Msk

#define SCB_DCCISW_LEVEL_Msk   (7UL << SCB_DCCISW_LEVEL_Pos)

SCB DCCISW: Level Mask

Definition at line 949 of file core_starmc1.h.

◆ SCB_DCCISW_WAY_Pos [8/8]

#define SCB_DCCISW_WAY_Pos   30U

SCB DCCISW: Way Position

Definition at line 951 of file core_starmc1.h.

◆ SCB_DCCISW_WAY_Msk [8/8]

#define SCB_DCCISW_WAY_Msk   (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 952 of file core_starmc1.h.

◆ SCB_DCCISW_SET_Pos [8/8]

#define SCB_DCCISW_SET_Pos   5U

SCB DCCISW: Set Position

Definition at line 954 of file core_starmc1.h.

◆ SCB_DCCISW_SET_Msk [8/8]

#define SCB_DCCISW_SET_Msk   (0xFFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 955 of file core_starmc1.h.

◆ SCB_ITCMCR_SZ_Pos [2/2]

#define SCB_ITCMCR_SZ_Pos   3U

SCB ITCMCR: SZ Position

Definition at line 959 of file core_starmc1.h.

◆ SCB_ITCMCR_SZ_Msk [2/2]

#define SCB_ITCMCR_SZ_Msk   (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 960 of file core_starmc1.h.

◆ SCB_ITCMCR_EN_Pos [2/2]

#define SCB_ITCMCR_EN_Pos   0U

SCB ITCMCR: EN Position

Definition at line 962 of file core_starmc1.h.

◆ SCB_ITCMCR_EN_Msk [2/2]

#define SCB_ITCMCR_EN_Msk   (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 963 of file core_starmc1.h.

◆ SCB_DTCMCR_SZ_Pos [2/2]

#define SCB_DTCMCR_SZ_Pos   3U

SCB DTCMCR: SZ Position

Definition at line 966 of file core_starmc1.h.

◆ SCB_DTCMCR_SZ_Msk [2/2]

#define SCB_DTCMCR_SZ_Msk   (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 967 of file core_starmc1.h.

◆ SCB_DTCMCR_EN_Pos [2/2]

#define SCB_DTCMCR_EN_Pos   0U

SCB DTCMCR: EN Position

Definition at line 969 of file core_starmc1.h.

◆ SCB_DTCMCR_EN_Msk [2/2]

#define SCB_DTCMCR_EN_Msk   (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 970 of file core_starmc1.h.

◆ SCB_CACR_DCCLEAN_Pos

#define SCB_CACR_DCCLEAN_Pos   16U

SCB CACR: DCCLEAN Position

Definition at line 973 of file core_starmc1.h.

◆ SCB_CACR_DCCLEAN_Msk

#define SCB_CACR_DCCLEAN_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: DCCLEAN Mask

Definition at line 974 of file core_starmc1.h.

◆ SCB_CACR_ICACTIVE_Pos

#define SCB_CACR_ICACTIVE_Pos   13U

SCB CACR: ICACTIVE Position

Definition at line 976 of file core_starmc1.h.

◆ SCB_CACR_ICACTIVE_Msk

#define SCB_CACR_ICACTIVE_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: ICACTIVE Mask

Definition at line 977 of file core_starmc1.h.

◆ SCB_CACR_DCACTIVE_Pos

#define SCB_CACR_DCACTIVE_Pos   12U

SCB CACR: DCACTIVE Position

Definition at line 979 of file core_starmc1.h.

◆ SCB_CACR_DCACTIVE_Msk

#define SCB_CACR_DCACTIVE_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: DCACTIVE Mask

Definition at line 980 of file core_starmc1.h.

◆ SCB_CACR_FORCEWT_Pos [2/2]

#define SCB_CACR_FORCEWT_Pos   2U

SCB CACR: FORCEWT Position

Definition at line 982 of file core_starmc1.h.

◆ SCB_CACR_FORCEWT_Msk [2/2]

#define SCB_CACR_FORCEWT_Msk   (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 983 of file core_starmc1.h.

◆ TPI_ACPR_SWOSCALER_Pos [1/5]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 1386 of file core_armv81mml.h.

◆ TPI_ACPR_SWOSCALER_Msk [1/5]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1387 of file core_armv81mml.h.

◆ TPI_FFCR_EnFmt_Pos [1/3]

#define TPI_FFCR_EnFmt_Pos   0U

TPI FFCR: EnFmt Position

Definition at line 1413 of file core_armv81mml.h.

◆ TPI_FFCR_EnFmt_Msk [1/3]

#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

TPI FFCR: EnFmt Mask

Definition at line 1414 of file core_armv81mml.h.

◆ TPI_PSCR_PSCount_Pos [1/5]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 1417 of file core_armv81mml.h.

◆ TPI_PSCR_PSCount_Msk [1/5]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1418 of file core_armv81mml.h.

◆ TPI_LSR_nTT_Pos [1/5]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1421 of file core_armv81mml.h.

◆ TPI_LSR_nTT_Msk [1/5]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1422 of file core_armv81mml.h.

◆ TPI_LSR_SLK_Pos [1/5]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 1424 of file core_armv81mml.h.

◆ TPI_LSR_SLK_Msk [1/5]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 1425 of file core_armv81mml.h.

◆ TPI_LSR_SLI_Pos [1/5]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 1427 of file core_armv81mml.h.

◆ TPI_LSR_SLI_Msk [1/5]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 1428 of file core_armv81mml.h.

◆ MPU_RLAR_PXN_Pos [1/3]

#define MPU_RLAR_PXN_Pos   4U

MPU RLAR: PXN Position

Definition at line 2346 of file core_armv81mml.h.

◆ MPU_RLAR_PXN_Msk [1/3]

#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)

MPU RLAR: PXN Mask

Definition at line 2347 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ16_Pos [1/3]

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

Definition at line 2562 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ16_Msk [1/3]

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

Definition at line 2563 of file core_armv81mml.h.

◆ FPU_FPDSCR_LTPSIZE_Pos [1/3]

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

Definition at line 2565 of file core_armv81mml.h.

◆ FPU_FPDSCR_LTPSIZE_Msk [1/3]

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

Definition at line 2566 of file core_armv81mml.h.

◆ FPU_MVFR0_FPRound_Pos [1/3]

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

Definition at line 2569 of file core_armv81mml.h.

◆ FPU_MVFR0_FPRound_Msk [1/3]

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

Definition at line 2570 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSqrt_Pos [1/3]

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

Definition at line 2572 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSqrt_Msk [1/3]

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

Definition at line 2573 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDivide_Pos [1/3]

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

Definition at line 2575 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDivide_Msk [1/3]

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

Definition at line 2576 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDP_Pos [1/3]

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

Definition at line 2578 of file core_armv81mml.h.

◆ FPU_MVFR0_FPDP_Msk [1/3]

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

Definition at line 2579 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSP_Pos [1/3]

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

Definition at line 2581 of file core_armv81mml.h.

◆ FPU_MVFR0_FPSP_Msk [1/3]

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

Definition at line 2582 of file core_armv81mml.h.

◆ FPU_MVFR0_SIMDReg_Pos [1/3]

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

Definition at line 2584 of file core_armv81mml.h.

◆ FPU_MVFR0_SIMDReg_Msk [1/3]

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

Definition at line 2585 of file core_armv81mml.h.

◆ FPU_MVFR1_FMAC_Pos [1/3]

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

Definition at line 2588 of file core_armv81mml.h.

◆ FPU_MVFR1_FMAC_Msk [1/3]

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

Definition at line 2589 of file core_armv81mml.h.

◆ FPU_MVFR1_FPHP_Pos [1/3]

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

Definition at line 2591 of file core_armv81mml.h.

◆ FPU_MVFR1_FPHP_Msk [1/3]

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

Definition at line 2592 of file core_armv81mml.h.

◆ FPU_MVFR1_FP16_Pos [1/3]

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

Definition at line 2594 of file core_armv81mml.h.

◆ FPU_MVFR1_FP16_Msk [1/3]

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

Definition at line 2595 of file core_armv81mml.h.

◆ FPU_MVFR1_MVE_Pos [1/3]

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

Definition at line 2597 of file core_armv81mml.h.

◆ FPU_MVFR1_MVE_Msk [1/3]

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

Definition at line 2598 of file core_armv81mml.h.

◆ FPU_MVFR1_FPDNaN_Pos [1/3]

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

Definition at line 2600 of file core_armv81mml.h.

◆ FPU_MVFR1_FPDNaN_Msk [1/3]

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

Definition at line 2601 of file core_armv81mml.h.

◆ FPU_MVFR1_FPFtZ_Pos [1/3]

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

Definition at line 2603 of file core_armv81mml.h.

◆ FPU_MVFR1_FPFtZ_Msk [1/3]

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

Definition at line 2604 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [1/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 2638 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [1/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 2639 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_FPD_Pos [1/3]

#define CoreDebug_DHCSR_S_FPD_Pos   23U
Deprecated
CoreDebug DHCSR: S_FPD Position
Deprecated
CoreDebug DHCSR: S_FPD Position
Deprecated
CoreDebug DHCSR: S_FPD Position

Definition at line 2647 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_FPD_Msk [1/3]

#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
Deprecated
CoreDebug DHCSR: S_FPD Mask
Deprecated
CoreDebug DHCSR: S_FPD Mask
Deprecated
CoreDebug DHCSR: S_FPD Mask

Definition at line 2648 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_SUIDE_Pos [1/3]

#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
Deprecated
CoreDebug DHCSR: S_SUIDE Position
Deprecated
CoreDebug DHCSR: S_SUIDE Position
Deprecated
CoreDebug DHCSR: S_SUIDE Position

Definition at line 2650 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_SUIDE_Msk [1/3]

#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_SUIDE Mask
Deprecated
CoreDebug DHCSR: S_SUIDE Mask
Deprecated
CoreDebug DHCSR: S_SUIDE Mask

Definition at line 2651 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_NSUIDE_Pos [1/3]

#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
Deprecated
CoreDebug DHCSR: S_NSUIDE Position
Deprecated
CoreDebug DHCSR: S_NSUIDE Position
Deprecated
CoreDebug DHCSR: S_NSUIDE Position

Definition at line 2653 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_NSUIDE_Msk [1/3]

#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask

Definition at line 2654 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_SDE_Pos [1/3]

#define CoreDebug_DHCSR_S_SDE_Pos   20U
Deprecated
CoreDebug DHCSR: S_SDE Position
Deprecated
CoreDebug DHCSR: S_SDE Position
Deprecated
CoreDebug DHCSR: S_SDE Position

Definition at line 2656 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_SDE_Msk [1/3]

#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
Deprecated
CoreDebug DHCSR: S_SDE Mask
Deprecated
CoreDebug DHCSR: S_SDE Mask
Deprecated
CoreDebug DHCSR: S_SDE Mask

Definition at line 2657 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_PMOV_Pos [1/3]

#define CoreDebug_DHCSR_C_PMOV_Pos   6U
Deprecated
CoreDebug DHCSR: C_PMOV Position
Deprecated
CoreDebug DHCSR: C_PMOV Position
Deprecated
CoreDebug DHCSR: C_PMOV Position

Definition at line 2671 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_PMOV_Msk [1/3]

#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
Deprecated
CoreDebug DHCSR: C_PMOV Mask
Deprecated
CoreDebug DHCSR: C_PMOV Mask
Deprecated
CoreDebug DHCSR: C_PMOV Mask

Definition at line 2672 of file core_armv81mml.h.

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Pos [1/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position

Definition at line 2737 of file core_armv81mml.h.

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Msk [1/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask

Definition at line 2738 of file core_armv81mml.h.

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Pos [1/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position

Definition at line 2740 of file core_armv81mml.h.

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Msk [1/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask

Definition at line 2741 of file core_armv81mml.h.

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Pos [1/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position

Definition at line 2743 of file core_armv81mml.h.

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Msk [1/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask

Definition at line 2744 of file core_armv81mml.h.

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Pos [1/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position

Definition at line 2746 of file core_armv81mml.h.

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Msk [1/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask

Definition at line 2747 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_UIDEN_Pos [1/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position

Definition at line 2750 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_UIDEN_Msk [1/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask

Definition at line 2751 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Pos [1/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position

Definition at line 2753 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Msk [1/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask

Definition at line 2754 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_FSDMA_Pos [1/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Position
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Position
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Position

Definition at line 2756 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_FSDMA_Msk [1/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Mask
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Mask
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Mask

Definition at line 2757 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [1/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 2759 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [1/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 2760 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [1/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 2762 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [1/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 2763 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [1/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 2765 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [1/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 2766 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [1/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 2768 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [1/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 2769 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_CDS_Pos [1/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

Definition at line 2772 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_CDS_Msk [1/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

Definition at line 2773 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [1/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

Definition at line 2775 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [1/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

Definition at line 2776 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [1/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

Definition at line 2778 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [1/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

Definition at line 2779 of file core_armv81mml.h.

◆ DCB_DHCSR_S_FPD_Pos [1/3]

#define DCB_DHCSR_S_FPD_Pos   23U

DCB DHCSR: Floating-point registers Debuggable Position

Definition at line 2818 of file core_armv81mml.h.

◆ DCB_DHCSR_S_FPD_Msk [1/3]

#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

Definition at line 2819 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SUIDE_Pos [1/3]

#define DCB_DHCSR_S_SUIDE_Pos   22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

Definition at line 2821 of file core_armv81mml.h.

◆ DCB_DHCSR_S_SUIDE_Msk [1/3]

#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

Definition at line 2822 of file core_armv81mml.h.

◆ DCB_DHCSR_S_NSUIDE_Pos [1/3]

#define DCB_DHCSR_S_NSUIDE_Pos   21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

Definition at line 2824 of file core_armv81mml.h.

◆ DCB_DHCSR_S_NSUIDE_Msk [1/3]

#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

Definition at line 2825 of file core_armv81mml.h.

◆ DCB_DHCSR_C_PMOV_Pos [1/3]

#define DCB_DHCSR_C_PMOV_Pos   6U

DCB DHCSR: Halt on PMU overflow control Position

Definition at line 2842 of file core_armv81mml.h.

◆ DCB_DHCSR_C_PMOV_Msk [1/3]

#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

Definition at line 2843 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Pos [1/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U

DCB DSCEMCR: Clear monitor request Position

Definition at line 2924 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Msk [1/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

Definition at line 2925 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Pos [1/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U

DCB DSCEMCR: Clear monitor pend Position

Definition at line 2927 of file core_armv81mml.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Msk [1/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

Definition at line 2928 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Pos [1/3]

#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U

DCB DSCEMCR: Set monitor request Position

Definition at line 2930 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Msk [1/3]

#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

Definition at line 2931 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Pos [1/3]

#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U

DCB DSCEMCR: Set monitor pend Position

Definition at line 2933 of file core_armv81mml.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Msk [1/3]

#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

Definition at line 2934 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDEN_Pos [1/3]

#define DCB_DAUTHCTRL_UIDEN_Pos   10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

Definition at line 2937 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDEN_Msk [1/3]

#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

Definition at line 2938 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [1/3]

#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

Definition at line 2940 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [1/3]

#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

Definition at line 2941 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_FSDMA_Pos [1/3]

#define DCB_DAUTHCTRL_FSDMA_Pos   8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

Definition at line 2943 of file core_armv81mml.h.

◆ DCB_DAUTHCTRL_FSDMA_Msk [1/3]

#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

Definition at line 2944 of file core_armv81mml.h.

◆ DIB_DAUTHSTATUS_SUNID_Pos [1/3]

#define DIB_DAUTHSTATUS_SUNID_Pos   22U

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position

Definition at line 3009 of file core_armv81mml.h.

◆ DIB_DAUTHSTATUS_SUNID_Msk [1/3]

#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask

Definition at line 3010 of file core_armv81mml.h.

◆ DIB_DAUTHSTATUS_SUID_Pos [1/3]

#define DIB_DAUTHSTATUS_SUID_Pos   20U

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position

Definition at line 3012 of file core_armv81mml.h.

◆ DIB_DAUTHSTATUS_SUID_Msk [1/3]

#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask

Definition at line 3013 of file core_armv81mml.h.

◆ DIB_DAUTHSTATUS_NSUNID_Pos [1/3]

#define DIB_DAUTHSTATUS_NSUNID_Pos   18U

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position

Definition at line 3015 of file core_armv81mml.h.

◆ DIB_DAUTHSTATUS_NSUNID_Msk [1/3]

#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask

Definition at line 3016 of file core_armv81mml.h.

◆ DIB_DAUTHSTATUS_NSUID_Pos [1/3]

#define DIB_DAUTHSTATUS_NSUID_Pos   16U

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position

Definition at line 3018 of file core_armv81mml.h.

◆ DIB_DAUTHSTATUS_NSUID_Msk [1/3]

#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask

Definition at line 3019 of file core_armv81mml.h.

◆ MPU_RBAR_ADDR_Pos [1/6]

#define MPU_RBAR_ADDR_Pos   8U

MPU RBAR: ADDR Position

Definition at line 560 of file core_cm0plus.h.

◆ MPU_RBAR_ADDR_Msk [1/6]

#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

Definition at line 561 of file core_cm0plus.h.

◆ MPU_RBAR_VALID_Pos [1/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

Definition at line 563 of file core_cm0plus.h.

◆ MPU_RBAR_VALID_Msk [1/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

Definition at line 564 of file core_cm0plus.h.

◆ MPU_RBAR_REGION_Pos [1/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

Definition at line 566 of file core_cm0plus.h.

◆ MPU_RBAR_REGION_Msk [1/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

Definition at line 567 of file core_cm0plus.h.

◆ MPU_RASR_ATTRS_Pos [1/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

Definition at line 570 of file core_cm0plus.h.

◆ MPU_RASR_ATTRS_Msk [1/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

Definition at line 571 of file core_cm0plus.h.

◆ MPU_RASR_XN_Pos [1/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

Definition at line 573 of file core_cm0plus.h.

◆ MPU_RASR_XN_Msk [1/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

Definition at line 574 of file core_cm0plus.h.

◆ MPU_RASR_AP_Pos [1/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

Definition at line 576 of file core_cm0plus.h.

◆ MPU_RASR_AP_Msk [1/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

Definition at line 577 of file core_cm0plus.h.

◆ MPU_RASR_TEX_Pos [1/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

Definition at line 579 of file core_cm0plus.h.

◆ MPU_RASR_TEX_Msk [1/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

Definition at line 580 of file core_cm0plus.h.

◆ MPU_RASR_S_Pos [1/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

Definition at line 582 of file core_cm0plus.h.

◆ MPU_RASR_S_Msk [1/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

Definition at line 583 of file core_cm0plus.h.

◆ MPU_RASR_C_Pos [1/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

Definition at line 585 of file core_cm0plus.h.

◆ MPU_RASR_C_Msk [1/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

Definition at line 586 of file core_cm0plus.h.

◆ MPU_RASR_B_Pos [1/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

Definition at line 588 of file core_cm0plus.h.

◆ MPU_RASR_B_Msk [1/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

Definition at line 589 of file core_cm0plus.h.

◆ MPU_RASR_SRD_Pos [1/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

Definition at line 591 of file core_cm0plus.h.

◆ MPU_RASR_SRD_Msk [1/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

Definition at line 592 of file core_cm0plus.h.

◆ MPU_RASR_SIZE_Pos [1/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

Definition at line 594 of file core_cm0plus.h.

◆ MPU_RASR_SIZE_Msk [1/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

Definition at line 595 of file core_cm0plus.h.

◆ MPU_RASR_ENABLE_Pos [1/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

Definition at line 597 of file core_cm0plus.h.

◆ MPU_RASR_ENABLE_Msk [1/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

Definition at line 598 of file core_cm0plus.h.

◆ ICB_ACTLR_DISCRITAXIRUW_Pos [1/2]

#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U

ACTLR: DISCRITAXIRUW Position

Definition at line 1012 of file core_cm55.h.

◆ ICB_ACTLR_DISCRITAXIRUW_Msk [1/2]

#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)

ACTLR: DISCRITAXIRUW Mask

Definition at line 1013 of file core_cm55.h.

◆ ICB_ACTLR_DISCRITAXIRUR_Pos [1/2]

#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U

ACTLR: DISCRITAXIRUR Position

Definition at line 1018 of file core_cm55.h.

◆ ICB_ACTLR_DISCRITAXIRUR_Msk [1/2]

#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)

ACTLR: DISCRITAXIRUR Mask

Definition at line 1019 of file core_cm55.h.

◆ ICB_ACTLR_EVENTBUSEN_Pos [1/2]

#define ICB_ACTLR_EVENTBUSEN_Pos   14U

ACTLR: EVENTBUSEN Position

Definition at line 1021 of file core_cm55.h.

◆ ICB_ACTLR_EVENTBUSEN_Msk [1/2]

#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)

ACTLR: EVENTBUSEN Mask

Definition at line 1022 of file core_cm55.h.

◆ ICB_ACTLR_EVENTBUSEN_S_Pos [1/2]

#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U

ACTLR: EVENTBUSEN_S Position

Definition at line 1024 of file core_cm55.h.

◆ ICB_ACTLR_EVENTBUSEN_S_Msk [1/2]

#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)

ACTLR: EVENTBUSEN_S Mask

Definition at line 1025 of file core_cm55.h.

◆ ICB_ACTLR_DISITMATBFLUSH_Pos [1/2]

#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U

ACTLR: DISITMATBFLUSH Position

Definition at line 1027 of file core_cm55.h.

◆ ICB_ACTLR_DISITMATBFLUSH_Msk [1/2]

#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)

ACTLR: DISITMATBFLUSH Mask

Definition at line 1028 of file core_cm55.h.

◆ ICB_ACTLR_DISNWAMODE_Pos [1/2]

#define ICB_ACTLR_DISNWAMODE_Pos   11U

ACTLR: DISNWAMODE Position

Definition at line 1030 of file core_cm55.h.

◆ ICB_ACTLR_DISNWAMODE_Msk [1/2]

#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)

ACTLR: DISNWAMODE Mask

Definition at line 1031 of file core_cm55.h.

◆ ICB_ACTLR_FPEXCODIS_Pos [1/2]

#define ICB_ACTLR_FPEXCODIS_Pos   10U

ACTLR: FPEXCODIS Position

Definition at line 1033 of file core_cm55.h.

◆ ICB_ACTLR_FPEXCODIS_Msk [1/2]

#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)

ACTLR: FPEXCODIS Mask

Definition at line 1034 of file core_cm55.h.

◆ ICB_ICTR_INTLINESNUM_Pos [1/2]

#define ICB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

Definition at line 1055 of file core_cm55.h.

◆ ICB_ICTR_INTLINESNUM_Msk [1/2]

#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 1056 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Pos [1/2]

#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U

MEMSYSCTL MSCR: CPWRDN Position

Definition at line 1431 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Msk [1/2]

#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)

MEMSYSCTL MSCR: CPWRDN Mask

Definition at line 1432 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Pos [1/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U

MEMSYSCTL MSCR: DCCLEAN Position

Definition at line 1434 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Msk [1/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)

MEMSYSCTL MSCR: DCCLEAN Mask

Definition at line 1435 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Pos [1/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U

MEMSYSCTL MSCR: ICACTIVE Position

Definition at line 1437 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Msk [1/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)

MEMSYSCTL MSCR: ICACTIVE Mask

Definition at line 1438 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Pos [1/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U

MEMSYSCTL MSCR: DCACTIVE Position

Definition at line 1440 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Msk [1/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)

MEMSYSCTL MSCR: DCACTIVE Mask

Definition at line 1441 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Pos [1/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U

MEMSYSCTL MSCR: EVECCFAULT Position

Definition at line 1446 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Msk [1/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)

MEMSYSCTL MSCR: EVECCFAULT Mask

Definition at line 1447 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Pos [1/2]

#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U

MEMSYSCTL MSCR: FORCEWT Position

Definition at line 1449 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Msk [1/2]

#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)

MEMSYSCTL MSCR: FORCEWT Mask

Definition at line 1450 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ECCEN_Pos [1/2]

#define MEMSYSCTL_MSCR_ECCEN_Pos   1U

MEMSYSCTL MSCR: ECCEN Position

Definition at line 1452 of file core_cm55.h.

◆ MEMSYSCTL_MSCR_ECCEN_Msk [1/2]

#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)

MEMSYSCTL MSCR: ECCEN Mask

Definition at line 1453 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_ENABLE_Pos [1/2]

#define MEMSYSCTL_PFCR_ENABLE_Pos   0U

MEMSYSCTL PFCR: ENABLE Position

Definition at line 1465 of file core_cm55.h.

◆ MEMSYSCTL_PFCR_ENABLE_Msk [1/2]

#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)

MEMSYSCTL PFCR: ENABLE Mask

Definition at line 1466 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_SZ_Pos [1/2]

#define MEMSYSCTL_ITCMCR_SZ_Pos   3U

MEMSYSCTL ITCMCR: SZ Position

Definition at line 1469 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_SZ_Msk [1/2]

#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)

MEMSYSCTL ITCMCR: SZ Mask

Definition at line 1470 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_EN_Pos [1/2]

#define MEMSYSCTL_ITCMCR_EN_Pos   0U

MEMSYSCTL ITCMCR: EN Position

Definition at line 1472 of file core_cm55.h.

◆ MEMSYSCTL_ITCMCR_EN_Msk [1/2]

#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)

MEMSYSCTL ITCMCR: EN Mask

Definition at line 1473 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_SZ_Pos [1/2]

#define MEMSYSCTL_DTCMCR_SZ_Pos   3U

MEMSYSCTL DTCMCR: SZ Position

Definition at line 1476 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_SZ_Msk [1/2]

#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)

MEMSYSCTL DTCMCR: SZ Mask

Definition at line 1477 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_EN_Pos [1/2]

#define MEMSYSCTL_DTCMCR_EN_Pos   0U

MEMSYSCTL DTCMCR: EN Position

Definition at line 1479 of file core_cm55.h.

◆ MEMSYSCTL_DTCMCR_EN_Msk [1/2]

#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)

MEMSYSCTL DTCMCR: EN Mask

Definition at line 1480 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_SZ_Pos [1/2]

#define MEMSYSCTL_PAHBCR_SZ_Pos   1U

MEMSYSCTL PAHBCR: SZ Position

Definition at line 1483 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_SZ_Msk [1/2]

#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)

MEMSYSCTL PAHBCR: SZ Mask

Definition at line 1484 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_EN_Pos [1/2]

#define MEMSYSCTL_PAHBCR_EN_Pos   0U

MEMSYSCTL PAHBCR: EN Position

Definition at line 1486 of file core_cm55.h.

◆ MEMSYSCTL_PAHBCR_EN_Msk [1/2]

#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)

MEMSYSCTL PAHBCR: EN Mask

Definition at line 1487 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Pos [1/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U

MEMSYSCTL ITGU_CTRL: DEREN Position

Definition at line 1490 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Msk [1/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)

MEMSYSCTL ITGU_CTRL: DEREN Mask

Definition at line 1491 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Pos [1/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL ITGU_CTRL: DBFEN Position

Definition at line 1493 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Msk [1/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL ITGU_CTRL: DBFEN Mask

Definition at line 1494 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U

MEMSYSCTL ITGU_CFG: PRESENT Position

Definition at line 1497 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)

MEMSYSCTL ITGU_CFG: PRESENT Mask

Definition at line 1498 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL ITGU_CFG: NUMBLKS Position

Definition at line 1500 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)

MEMSYSCTL ITGU_CFG: NUMBLKS Mask

Definition at line 1501 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Pos [1/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL ITGU_CFG: BLKSZ Position

Definition at line 1503 of file core_cm55.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Msk [1/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL ITGU_CFG: BLKSZ Mask

Definition at line 1504 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Pos [1/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U

MEMSYSCTL DTGU_CTRL: DEREN Position

Definition at line 1507 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Msk [1/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)

MEMSYSCTL DTGU_CTRL: DEREN Mask

Definition at line 1508 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Pos [1/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL DTGU_CTRL: DBFEN Position

Definition at line 1510 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Msk [1/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL DTGU_CTRL: DBFEN Mask

Definition at line 1511 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U

MEMSYSCTL DTGU_CFG: PRESENT Position

Definition at line 1514 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)

MEMSYSCTL DTGU_CFG: PRESENT Mask

Definition at line 1515 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL DTGU_CFG: NUMBLKS Position

Definition at line 1517 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)

MEMSYSCTL DTGU_CFG: NUMBLKS Mask

Definition at line 1518 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Pos [1/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL DTGU_CFG: BLKSZ Position

Definition at line 1520 of file core_cm55.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Msk [1/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL DTGU_CFG: BLKSZ Mask

Definition at line 1521 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos [1/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U

PWRMODCTL CPDLPSTATE: RLPSTATE Position

Definition at line 1544 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk [1/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)

PWRMODCTL CPDLPSTATE: RLPSTATE Mask

Definition at line 1545 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos [1/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U

PWRMODCTL CPDLPSTATE: ELPSTATE Position

Definition at line 1547 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk [1/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)

PWRMODCTL CPDLPSTATE: ELPSTATE Mask

Definition at line 1548 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos [1/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U

PWRMODCTL CPDLPSTATE: CLPSTATE Position

Definition at line 1550 of file core_cm55.h.

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk [1/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)

PWRMODCTL CPDLPSTATE: CLPSTATE Mask

Definition at line 1551 of file core_cm55.h.

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos [1/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U

PWRMODCTL DPDLPSTATE: DLPSTATE Position

Definition at line 1554 of file core_cm55.h.

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk [1/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)

PWRMODCTL DPDLPSTATE: DLPSTATE Mask

Definition at line 1555 of file core_cm55.h.

◆ EWIC_EVENTSPR_EDBGREQ_Pos [1/2]

#define EWIC_EVENTSPR_EDBGREQ_Pos   2U

EWIC EVENTSPR: EDBGREQ Position

Definition at line 1579 of file core_cm55.h.

◆ EWIC_EVENTSPR_EDBGREQ_Msk [1/2]

#define EWIC_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)

EWIC EVENTSPR: EDBGREQ Mask

Definition at line 1580 of file core_cm55.h.

◆ EWIC_EVENTSPR_NMI_Pos [1/2]

#define EWIC_EVENTSPR_NMI_Pos   1U

EWIC EVENTSPR: NMI Position

Definition at line 1582 of file core_cm55.h.

◆ EWIC_EVENTSPR_NMI_Msk [1/2]

#define EWIC_EVENTSPR_NMI_Msk   (0x1UL << EWIC_EVENTSPR_NMI_Pos)

EWIC EVENTSPR: NMI Mask

Definition at line 1583 of file core_cm55.h.

◆ EWIC_EVENTSPR_EVENT_Pos [1/2]

#define EWIC_EVENTSPR_EVENT_Pos   0U

EWIC EVENTSPR: EVENT Position

Definition at line 1585 of file core_cm55.h.

◆ EWIC_EVENTSPR_EVENT_Msk [1/2]

#define EWIC_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/)

EWIC EVENTSPR: EVENT Mask

Definition at line 1586 of file core_cm55.h.

◆ EWIC_EVENTMASKA_EDBGREQ_Pos [1/2]

#define EWIC_EVENTMASKA_EDBGREQ_Pos   2U

EWIC EVENTMASKA: EDBGREQ Position

Definition at line 1589 of file core_cm55.h.

◆ EWIC_EVENTMASKA_EDBGREQ_Msk [1/2]

#define EWIC_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)

EWIC EVENTMASKA: EDBGREQ Mask

Definition at line 1590 of file core_cm55.h.

◆ EWIC_EVENTMASKA_NMI_Pos [1/2]

#define EWIC_EVENTMASKA_NMI_Pos   1U

EWIC EVENTMASKA: NMI Position

Definition at line 1592 of file core_cm55.h.

◆ EWIC_EVENTMASKA_NMI_Msk [1/2]

#define EWIC_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_EVENTMASKA_NMI_Pos)

EWIC EVENTMASKA: NMI Mask

Definition at line 1593 of file core_cm55.h.

◆ EWIC_EVENTMASKA_EVENT_Pos [1/2]

#define EWIC_EVENTMASKA_EVENT_Pos   0U

EWIC EVENTMASKA: EVENT Position

Definition at line 1595 of file core_cm55.h.

◆ EWIC_EVENTMASKA_EVENT_Msk [1/2]

#define EWIC_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/)

EWIC EVENTMASKA: EVENT Mask

Definition at line 1596 of file core_cm55.h.

◆ EWIC_EVENTMASK_IRQ_Pos [1/2]

#define EWIC_EVENTMASK_IRQ_Pos   0U

EWIC EVENTMASKA: IRQ Position

Definition at line 1599 of file core_cm55.h.

◆ EWIC_EVENTMASK_IRQ_Msk [1/2]

#define EWIC_EVENTMASK_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/)

EWIC EVENTMASKA: IRQ Mask

Definition at line 1600 of file core_cm55.h.

◆ ERRBNK_IEBR0_SWDEF_Pos [1/2]

#define ERRBNK_IEBR0_SWDEF_Pos   30U

ERRBNK IEBR0: SWDEF Position

Definition at line 1629 of file core_cm55.h.

◆ ERRBNK_IEBR0_SWDEF_Msk [1/2]

#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)

ERRBNK IEBR0: SWDEF Mask

Definition at line 1630 of file core_cm55.h.

◆ ERRBNK_IEBR0_BANK_Pos [1/2]

#define ERRBNK_IEBR0_BANK_Pos   16U

ERRBNK IEBR0: BANK Position

Definition at line 1632 of file core_cm55.h.

◆ ERRBNK_IEBR0_BANK_Msk [1/2]

#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)

ERRBNK IEBR0: BANK Mask

Definition at line 1633 of file core_cm55.h.

◆ ERRBNK_IEBR0_LOCATION_Pos [1/2]

#define ERRBNK_IEBR0_LOCATION_Pos   2U

ERRBNK IEBR0: LOCATION Position

Definition at line 1635 of file core_cm55.h.

◆ ERRBNK_IEBR0_LOCATION_Msk [1/2]

#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)

ERRBNK IEBR0: LOCATION Mask

Definition at line 1636 of file core_cm55.h.

◆ ERRBNK_IEBR0_LOCKED_Pos [1/2]

#define ERRBNK_IEBR0_LOCKED_Pos   1U

ERRBNK IEBR0: LOCKED Position

Definition at line 1638 of file core_cm55.h.

◆ ERRBNK_IEBR0_LOCKED_Msk [1/2]

#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)

ERRBNK IEBR0: LOCKED Mask

Definition at line 1639 of file core_cm55.h.

◆ ERRBNK_IEBR0_VALID_Pos [1/2]

#define ERRBNK_IEBR0_VALID_Pos   0U

ERRBNK IEBR0: VALID Position

Definition at line 1641 of file core_cm55.h.

◆ ERRBNK_IEBR0_VALID_Msk [1/2]

#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)

ERRBNK IEBR0: VALID Mask

Definition at line 1642 of file core_cm55.h.

◆ ERRBNK_IEBR1_SWDEF_Pos [1/2]

#define ERRBNK_IEBR1_SWDEF_Pos   30U

ERRBNK IEBR1: SWDEF Position

Definition at line 1645 of file core_cm55.h.

◆ ERRBNK_IEBR1_SWDEF_Msk [1/2]

#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)

ERRBNK IEBR1: SWDEF Mask

Definition at line 1646 of file core_cm55.h.

◆ ERRBNK_IEBR1_BANK_Pos [1/2]

#define ERRBNK_IEBR1_BANK_Pos   16U

ERRBNK IEBR1: BANK Position

Definition at line 1648 of file core_cm55.h.

◆ ERRBNK_IEBR1_BANK_Msk [1/2]

#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)

ERRBNK IEBR1: BANK Mask

Definition at line 1649 of file core_cm55.h.

◆ ERRBNK_IEBR1_LOCATION_Pos [1/2]

#define ERRBNK_IEBR1_LOCATION_Pos   2U

ERRBNK IEBR1: LOCATION Position

Definition at line 1651 of file core_cm55.h.

◆ ERRBNK_IEBR1_LOCATION_Msk [1/2]

#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)

ERRBNK IEBR1: LOCATION Mask

Definition at line 1652 of file core_cm55.h.

◆ ERRBNK_IEBR1_LOCKED_Pos [1/2]

#define ERRBNK_IEBR1_LOCKED_Pos   1U

ERRBNK IEBR1: LOCKED Position

Definition at line 1654 of file core_cm55.h.

◆ ERRBNK_IEBR1_LOCKED_Msk [1/2]

#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)

ERRBNK IEBR1: LOCKED Mask

Definition at line 1655 of file core_cm55.h.

◆ ERRBNK_IEBR1_VALID_Pos [1/2]

#define ERRBNK_IEBR1_VALID_Pos   0U

ERRBNK IEBR1: VALID Position

Definition at line 1657 of file core_cm55.h.

◆ ERRBNK_IEBR1_VALID_Msk [1/2]

#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)

ERRBNK IEBR1: VALID Mask

Definition at line 1658 of file core_cm55.h.

◆ ERRBNK_DEBR0_SWDEF_Pos [1/2]

#define ERRBNK_DEBR0_SWDEF_Pos   30U

ERRBNK DEBR0: SWDEF Position

Definition at line 1661 of file core_cm55.h.

◆ ERRBNK_DEBR0_SWDEF_Msk [1/2]

#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)

ERRBNK DEBR0: SWDEF Mask

Definition at line 1662 of file core_cm55.h.

◆ ERRBNK_DEBR0_TYPE_Pos [1/2]

#define ERRBNK_DEBR0_TYPE_Pos   17U

ERRBNK DEBR0: TYPE Position

Definition at line 1664 of file core_cm55.h.

◆ ERRBNK_DEBR0_TYPE_Msk [1/2]

#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)

ERRBNK DEBR0: TYPE Mask

Definition at line 1665 of file core_cm55.h.

◆ ERRBNK_DEBR0_BANK_Pos [1/2]

#define ERRBNK_DEBR0_BANK_Pos   16U

ERRBNK DEBR0: BANK Position

Definition at line 1667 of file core_cm55.h.

◆ ERRBNK_DEBR0_BANK_Msk [1/2]

#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)

ERRBNK DEBR0: BANK Mask

Definition at line 1668 of file core_cm55.h.

◆ ERRBNK_DEBR0_LOCATION_Pos [1/2]

#define ERRBNK_DEBR0_LOCATION_Pos   2U

ERRBNK DEBR0: LOCATION Position

Definition at line 1670 of file core_cm55.h.

◆ ERRBNK_DEBR0_LOCATION_Msk [1/2]

#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)

ERRBNK DEBR0: LOCATION Mask

Definition at line 1671 of file core_cm55.h.

◆ ERRBNK_DEBR0_LOCKED_Pos [1/2]

#define ERRBNK_DEBR0_LOCKED_Pos   1U

ERRBNK DEBR0: LOCKED Position

Definition at line 1673 of file core_cm55.h.

◆ ERRBNK_DEBR0_LOCKED_Msk [1/2]

#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)

ERRBNK DEBR0: LOCKED Mask

Definition at line 1674 of file core_cm55.h.

◆ ERRBNK_DEBR0_VALID_Pos [1/2]

#define ERRBNK_DEBR0_VALID_Pos   0U

ERRBNK DEBR0: VALID Position

Definition at line 1676 of file core_cm55.h.

◆ ERRBNK_DEBR0_VALID_Msk [1/2]

#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)

ERRBNK DEBR0: VALID Mask

Definition at line 1677 of file core_cm55.h.

◆ ERRBNK_DEBR1_SWDEF_Pos [1/2]

#define ERRBNK_DEBR1_SWDEF_Pos   30U

ERRBNK DEBR1: SWDEF Position

Definition at line 1680 of file core_cm55.h.

◆ ERRBNK_DEBR1_SWDEF_Msk [1/2]

#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)

ERRBNK DEBR1: SWDEF Mask

Definition at line 1681 of file core_cm55.h.

◆ ERRBNK_DEBR1_TYPE_Pos [1/2]

#define ERRBNK_DEBR1_TYPE_Pos   17U

ERRBNK DEBR1: TYPE Position

Definition at line 1683 of file core_cm55.h.

◆ ERRBNK_DEBR1_TYPE_Msk [1/2]

#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)

ERRBNK DEBR1: TYPE Mask

Definition at line 1684 of file core_cm55.h.

◆ ERRBNK_DEBR1_BANK_Pos [1/2]

#define ERRBNK_DEBR1_BANK_Pos   16U

ERRBNK DEBR1: BANK Position

Definition at line 1686 of file core_cm55.h.

◆ ERRBNK_DEBR1_BANK_Msk [1/2]

#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)

ERRBNK DEBR1: BANK Mask

Definition at line 1687 of file core_cm55.h.

◆ ERRBNK_DEBR1_LOCATION_Pos [1/2]

#define ERRBNK_DEBR1_LOCATION_Pos   2U

ERRBNK DEBR1: LOCATION Position

Definition at line 1689 of file core_cm55.h.

◆ ERRBNK_DEBR1_LOCATION_Msk [1/2]

#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)

ERRBNK DEBR1: LOCATION Mask

Definition at line 1690 of file core_cm55.h.

◆ ERRBNK_DEBR1_LOCKED_Pos [1/2]

#define ERRBNK_DEBR1_LOCKED_Pos   1U

ERRBNK DEBR1: LOCKED Position

Definition at line 1692 of file core_cm55.h.

◆ ERRBNK_DEBR1_LOCKED_Msk [1/2]

#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)

ERRBNK DEBR1: LOCKED Mask

Definition at line 1693 of file core_cm55.h.

◆ ERRBNK_DEBR1_VALID_Pos [1/2]

#define ERRBNK_DEBR1_VALID_Pos   0U

ERRBNK DEBR1: VALID Position

Definition at line 1695 of file core_cm55.h.

◆ ERRBNK_DEBR1_VALID_Msk [1/2]

#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)

ERRBNK DEBR1: VALID Mask

Definition at line 1696 of file core_cm55.h.

◆ ERRBNK_TEBR0_SWDEF_Pos [1/2]

#define ERRBNK_TEBR0_SWDEF_Pos   30U

ERRBNK TEBR0: SWDEF Position

Definition at line 1699 of file core_cm55.h.

◆ ERRBNK_TEBR0_SWDEF_Msk [1/2]

#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)

ERRBNK TEBR0: SWDEF Mask

Definition at line 1700 of file core_cm55.h.

◆ ERRBNK_TEBR0_POISON_Pos [1/2]

#define ERRBNK_TEBR0_POISON_Pos   28U

ERRBNK TEBR0: POISON Position

Definition at line 1702 of file core_cm55.h.

◆ ERRBNK_TEBR0_POISON_Msk [1/2]

#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)

ERRBNK TEBR0: POISON Mask

Definition at line 1703 of file core_cm55.h.

◆ ERRBNK_TEBR0_TYPE_Pos [1/2]

#define ERRBNK_TEBR0_TYPE_Pos   27U

ERRBNK TEBR0: TYPE Position

Definition at line 1705 of file core_cm55.h.

◆ ERRBNK_TEBR0_TYPE_Msk [1/2]

#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)

ERRBNK TEBR0: TYPE Mask

Definition at line 1706 of file core_cm55.h.

◆ ERRBNK_TEBR0_BANK_Pos [1/2]

#define ERRBNK_TEBR0_BANK_Pos   24U

ERRBNK TEBR0: BANK Position

Definition at line 1708 of file core_cm55.h.

◆ ERRBNK_TEBR0_BANK_Msk [1/2]

#define ERRBNK_TEBR0_BANK_Msk   (0x3UL << ERRBNK_TEBR0_BANK_Pos)

ERRBNK TEBR0: BANK Mask

Definition at line 1709 of file core_cm55.h.

◆ ERRBNK_TEBR0_LOCATION_Pos [1/2]

#define ERRBNK_TEBR0_LOCATION_Pos   2U

ERRBNK TEBR0: LOCATION Position

Definition at line 1711 of file core_cm55.h.

◆ ERRBNK_TEBR0_LOCATION_Msk [1/2]

#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)

ERRBNK TEBR0: LOCATION Mask

Definition at line 1712 of file core_cm55.h.

◆ ERRBNK_TEBR0_LOCKED_Pos [1/2]

#define ERRBNK_TEBR0_LOCKED_Pos   1U

ERRBNK TEBR0: LOCKED Position

Definition at line 1714 of file core_cm55.h.

◆ ERRBNK_TEBR0_LOCKED_Msk [1/2]

#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)

ERRBNK TEBR0: LOCKED Mask

Definition at line 1715 of file core_cm55.h.

◆ ERRBNK_TEBR0_VALID_Pos [1/2]

#define ERRBNK_TEBR0_VALID_Pos   0U

ERRBNK TEBR0: VALID Position

Definition at line 1717 of file core_cm55.h.

◆ ERRBNK_TEBR0_VALID_Msk [1/2]

#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)

ERRBNK TEBR0: VALID Mask

Definition at line 1718 of file core_cm55.h.

◆ ERRBNK_TEBR1_SWDEF_Pos [1/2]

#define ERRBNK_TEBR1_SWDEF_Pos   30U

ERRBNK TEBR1: SWDEF Position

Definition at line 1721 of file core_cm55.h.

◆ ERRBNK_TEBR1_SWDEF_Msk [1/2]

#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)

ERRBNK TEBR1: SWDEF Mask

Definition at line 1722 of file core_cm55.h.

◆ ERRBNK_TEBR1_POISON_Pos [1/2]

#define ERRBNK_TEBR1_POISON_Pos   28U

ERRBNK TEBR1: POISON Position

Definition at line 1724 of file core_cm55.h.

◆ ERRBNK_TEBR1_POISON_Msk [1/2]

#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)

ERRBNK TEBR1: POISON Mask

Definition at line 1725 of file core_cm55.h.

◆ ERRBNK_TEBR1_TYPE_Pos [1/2]

#define ERRBNK_TEBR1_TYPE_Pos   27U

ERRBNK TEBR1: TYPE Position

Definition at line 1727 of file core_cm55.h.

◆ ERRBNK_TEBR1_TYPE_Msk [1/2]

#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)

ERRBNK TEBR1: TYPE Mask

Definition at line 1728 of file core_cm55.h.

◆ ERRBNK_TEBR1_BANK_Pos [1/2]

#define ERRBNK_TEBR1_BANK_Pos   24U

ERRBNK TEBR1: BANK Position

Definition at line 1730 of file core_cm55.h.

◆ ERRBNK_TEBR1_BANK_Msk [1/2]

#define ERRBNK_TEBR1_BANK_Msk   (0x3UL << ERRBNK_TEBR1_BANK_Pos)

ERRBNK TEBR1: BANK Mask

Definition at line 1731 of file core_cm55.h.

◆ ERRBNK_TEBR1_LOCATION_Pos [1/2]

#define ERRBNK_TEBR1_LOCATION_Pos   2U

ERRBNK TEBR1: LOCATION Position

Definition at line 1733 of file core_cm55.h.

◆ ERRBNK_TEBR1_LOCATION_Msk [1/2]

#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)

ERRBNK TEBR1: LOCATION Mask

Definition at line 1734 of file core_cm55.h.

◆ ERRBNK_TEBR1_LOCKED_Pos [1/2]

#define ERRBNK_TEBR1_LOCKED_Pos   1U

ERRBNK TEBR1: LOCKED Position

Definition at line 1736 of file core_cm55.h.

◆ ERRBNK_TEBR1_LOCKED_Msk [1/2]

#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)

ERRBNK TEBR1: LOCKED Mask

Definition at line 1737 of file core_cm55.h.

◆ ERRBNK_TEBR1_VALID_Pos [1/2]

#define ERRBNK_TEBR1_VALID_Pos   0U

ERRBNK TEBR1: VALID Position

Definition at line 1739 of file core_cm55.h.

◆ ERRBNK_TEBR1_VALID_Msk [1/2]

#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)

ERRBNK TEBR1: VALID Mask

Definition at line 1740 of file core_cm55.h.

◆ TPI_ACPR_SWOSCALER_Pos [2/5]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 1881 of file core_cm55.h.

◆ TPI_ACPR_SWOSCALER_Msk [2/5]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1882 of file core_cm55.h.

◆ TPI_FFCR_EnFmt_Pos [2/3]

#define TPI_FFCR_EnFmt_Pos   0U

TPI FFCR: EnFmt Position

Definition at line 1908 of file core_cm55.h.

◆ TPI_FFCR_EnFmt_Msk [2/3]

#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

TPI FFCR: EnFmt Mask

Definition at line 1909 of file core_cm55.h.

◆ TPI_PSCR_PSCount_Pos [2/5]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 1912 of file core_cm55.h.

◆ TPI_PSCR_PSCount_Msk [2/5]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1913 of file core_cm55.h.

◆ TPI_LSR_nTT_Pos [2/5]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1916 of file core_cm55.h.

◆ TPI_LSR_nTT_Msk [2/5]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1917 of file core_cm55.h.

◆ TPI_LSR_SLK_Pos [2/5]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 1919 of file core_cm55.h.

◆ TPI_LSR_SLK_Msk [2/5]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 1920 of file core_cm55.h.

◆ TPI_LSR_SLI_Pos [2/5]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 1922 of file core_cm55.h.

◆ TPI_LSR_SLI_Msk [2/5]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 1923 of file core_cm55.h.

◆ MPU_RLAR_PXN_Pos [2/3]

#define MPU_RLAR_PXN_Pos   4U

MPU RLAR: PXN Position

Definition at line 2842 of file core_cm55.h.

◆ MPU_RLAR_PXN_Msk [2/3]

#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)

MPU RLAR: PXN Mask

Definition at line 2843 of file core_cm55.h.

◆ FPU_FPDSCR_FZ16_Pos [2/3]

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

Definition at line 3058 of file core_cm55.h.

◆ FPU_FPDSCR_FZ16_Msk [2/3]

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

Definition at line 3059 of file core_cm55.h.

◆ FPU_FPDSCR_LTPSIZE_Pos [2/3]

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

Definition at line 3061 of file core_cm55.h.

◆ FPU_FPDSCR_LTPSIZE_Msk [2/3]

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

Definition at line 3062 of file core_cm55.h.

◆ FPU_MVFR0_FPRound_Pos [2/3]

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

Definition at line 3065 of file core_cm55.h.

◆ FPU_MVFR0_FPRound_Msk [2/3]

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

Definition at line 3066 of file core_cm55.h.

◆ FPU_MVFR0_FPSqrt_Pos [2/3]

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

Definition at line 3068 of file core_cm55.h.

◆ FPU_MVFR0_FPSqrt_Msk [2/3]

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

Definition at line 3069 of file core_cm55.h.

◆ FPU_MVFR0_FPDivide_Pos [2/3]

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

Definition at line 3071 of file core_cm55.h.

◆ FPU_MVFR0_FPDivide_Msk [2/3]

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

Definition at line 3072 of file core_cm55.h.

◆ FPU_MVFR0_FPDP_Pos [2/3]

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

Definition at line 3074 of file core_cm55.h.

◆ FPU_MVFR0_FPDP_Msk [2/3]

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

Definition at line 3075 of file core_cm55.h.

◆ FPU_MVFR0_FPSP_Pos [2/3]

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

Definition at line 3077 of file core_cm55.h.

◆ FPU_MVFR0_FPSP_Msk [2/3]

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

Definition at line 3078 of file core_cm55.h.

◆ FPU_MVFR0_SIMDReg_Pos [2/3]

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

Definition at line 3080 of file core_cm55.h.

◆ FPU_MVFR0_SIMDReg_Msk [2/3]

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

Definition at line 3081 of file core_cm55.h.

◆ FPU_MVFR1_FMAC_Pos [2/3]

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

Definition at line 3084 of file core_cm55.h.

◆ FPU_MVFR1_FMAC_Msk [2/3]

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

Definition at line 3085 of file core_cm55.h.

◆ FPU_MVFR1_FPHP_Pos [2/3]

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

Definition at line 3087 of file core_cm55.h.

◆ FPU_MVFR1_FPHP_Msk [2/3]

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

Definition at line 3088 of file core_cm55.h.

◆ FPU_MVFR1_FP16_Pos [2/3]

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

Definition at line 3090 of file core_cm55.h.

◆ FPU_MVFR1_FP16_Msk [2/3]

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

Definition at line 3091 of file core_cm55.h.

◆ FPU_MVFR1_MVE_Pos [2/3]

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

Definition at line 3093 of file core_cm55.h.

◆ FPU_MVFR1_MVE_Msk [2/3]

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

Definition at line 3094 of file core_cm55.h.

◆ FPU_MVFR1_FPDNaN_Pos [2/3]

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

Definition at line 3096 of file core_cm55.h.

◆ FPU_MVFR1_FPDNaN_Msk [2/3]

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

Definition at line 3097 of file core_cm55.h.

◆ FPU_MVFR1_FPFtZ_Pos [2/3]

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

Definition at line 3099 of file core_cm55.h.

◆ FPU_MVFR1_FPFtZ_Msk [2/3]

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

Definition at line 3100 of file core_cm55.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [2/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 3134 of file core_cm55.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [2/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 3135 of file core_cm55.h.

◆ CoreDebug_DHCSR_S_FPD_Pos [2/3]

#define CoreDebug_DHCSR_S_FPD_Pos   23U
Deprecated
CoreDebug DHCSR: S_FPD Position
Deprecated
CoreDebug DHCSR: S_FPD Position

Definition at line 3143 of file core_cm55.h.

◆ CoreDebug_DHCSR_S_FPD_Msk [2/3]

#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
Deprecated
CoreDebug DHCSR: S_FPD Mask
Deprecated
CoreDebug DHCSR: S_FPD Mask

Definition at line 3144 of file core_cm55.h.

◆ CoreDebug_DHCSR_S_SUIDE_Pos [2/3]

#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
Deprecated
CoreDebug DHCSR: S_SUIDE Position
Deprecated
CoreDebug DHCSR: S_SUIDE Position

Definition at line 3146 of file core_cm55.h.

◆ CoreDebug_DHCSR_S_SUIDE_Msk [2/3]

#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_SUIDE Mask
Deprecated
CoreDebug DHCSR: S_SUIDE Mask

Definition at line 3147 of file core_cm55.h.

◆ CoreDebug_DHCSR_S_NSUIDE_Pos [2/3]

#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
Deprecated
CoreDebug DHCSR: S_NSUIDE Position
Deprecated
CoreDebug DHCSR: S_NSUIDE Position

Definition at line 3149 of file core_cm55.h.

◆ CoreDebug_DHCSR_S_NSUIDE_Msk [2/3]

#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask

Definition at line 3150 of file core_cm55.h.

◆ CoreDebug_DHCSR_S_SDE_Pos [2/3]

#define CoreDebug_DHCSR_S_SDE_Pos   20U
Deprecated
CoreDebug DHCSR: S_SDE Position
Deprecated
CoreDebug DHCSR: S_SDE Position

Definition at line 3152 of file core_cm55.h.

◆ CoreDebug_DHCSR_S_SDE_Msk [2/3]

#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
Deprecated
CoreDebug DHCSR: S_SDE Mask
Deprecated
CoreDebug DHCSR: S_SDE Mask

Definition at line 3153 of file core_cm55.h.

◆ CoreDebug_DHCSR_C_PMOV_Pos [2/3]

#define CoreDebug_DHCSR_C_PMOV_Pos   6U
Deprecated
CoreDebug DHCSR: C_PMOV Position
Deprecated
CoreDebug DHCSR: C_PMOV Position

Definition at line 3167 of file core_cm55.h.

◆ CoreDebug_DHCSR_C_PMOV_Msk [2/3]

#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
Deprecated
CoreDebug DHCSR: C_PMOV Mask
Deprecated
CoreDebug DHCSR: C_PMOV Mask

Definition at line 3168 of file core_cm55.h.

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Pos [2/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position

Definition at line 3233 of file core_cm55.h.

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Msk [2/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask

Definition at line 3234 of file core_cm55.h.

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Pos [2/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position

Definition at line 3236 of file core_cm55.h.

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Msk [2/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask

Definition at line 3237 of file core_cm55.h.

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Pos [2/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position

Definition at line 3239 of file core_cm55.h.

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Msk [2/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask

Definition at line 3240 of file core_cm55.h.

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Pos [2/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position

Definition at line 3242 of file core_cm55.h.

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Msk [2/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask

Definition at line 3243 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_UIDEN_Pos [2/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position

Definition at line 3246 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_UIDEN_Msk [2/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask

Definition at line 3247 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Pos [2/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position

Definition at line 3249 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Msk [2/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask

Definition at line 3250 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_FSDMA_Pos [2/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Position
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Position

Definition at line 3252 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_FSDMA_Msk [2/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Mask
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Mask

Definition at line 3253 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [2/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 3255 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [2/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 3256 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [2/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 3258 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [2/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 3259 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [2/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 3261 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [2/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 3262 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [2/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 3264 of file core_cm55.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [2/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 3265 of file core_cm55.h.

◆ CoreDebug_DSCSR_CDS_Pos [2/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

Definition at line 3268 of file core_cm55.h.

◆ CoreDebug_DSCSR_CDS_Msk [2/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

Definition at line 3269 of file core_cm55.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [2/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

Definition at line 3271 of file core_cm55.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [2/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

Definition at line 3272 of file core_cm55.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [2/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

Definition at line 3274 of file core_cm55.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [2/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

Definition at line 3275 of file core_cm55.h.

◆ DCB_DHCSR_S_FPD_Pos [2/3]

#define DCB_DHCSR_S_FPD_Pos   23U

DCB DHCSR: Floating-point registers Debuggable Position

Definition at line 3314 of file core_cm55.h.

◆ DCB_DHCSR_S_FPD_Msk [2/3]

#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

Definition at line 3315 of file core_cm55.h.

◆ DCB_DHCSR_S_SUIDE_Pos [2/3]

#define DCB_DHCSR_S_SUIDE_Pos   22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

Definition at line 3317 of file core_cm55.h.

◆ DCB_DHCSR_S_SUIDE_Msk [2/3]

#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

Definition at line 3318 of file core_cm55.h.

◆ DCB_DHCSR_S_NSUIDE_Pos [2/3]

#define DCB_DHCSR_S_NSUIDE_Pos   21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

Definition at line 3320 of file core_cm55.h.

◆ DCB_DHCSR_S_NSUIDE_Msk [2/3]

#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

Definition at line 3321 of file core_cm55.h.

◆ DCB_DHCSR_C_PMOV_Pos [2/3]

#define DCB_DHCSR_C_PMOV_Pos   6U

DCB DHCSR: Halt on PMU overflow control Position

Definition at line 3338 of file core_cm55.h.

◆ DCB_DHCSR_C_PMOV_Msk [2/3]

#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

Definition at line 3339 of file core_cm55.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Pos [2/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U

DCB DSCEMCR: Clear monitor request Position

Definition at line 3420 of file core_cm55.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Msk [2/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

Definition at line 3421 of file core_cm55.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Pos [2/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U

DCB DSCEMCR: Clear monitor pend Position

Definition at line 3423 of file core_cm55.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Msk [2/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

Definition at line 3424 of file core_cm55.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Pos [2/3]

#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U

DCB DSCEMCR: Set monitor request Position

Definition at line 3426 of file core_cm55.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Msk [2/3]

#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

Definition at line 3427 of file core_cm55.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Pos [2/3]

#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U

DCB DSCEMCR: Set monitor pend Position

Definition at line 3429 of file core_cm55.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Msk [2/3]

#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

Definition at line 3430 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDEN_Pos [2/3]

#define DCB_DAUTHCTRL_UIDEN_Pos   10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

Definition at line 3433 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDEN_Msk [2/3]

#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

Definition at line 3434 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [2/3]

#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

Definition at line 3436 of file core_cm55.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [2/3]

#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

Definition at line 3437 of file core_cm55.h.

◆ DCB_DAUTHCTRL_FSDMA_Pos [2/3]

#define DCB_DAUTHCTRL_FSDMA_Pos   8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

Definition at line 3439 of file core_cm55.h.

◆ DCB_DAUTHCTRL_FSDMA_Msk [2/3]

#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

Definition at line 3440 of file core_cm55.h.

◆ DIB_DAUTHSTATUS_SUNID_Pos [2/3]

#define DIB_DAUTHSTATUS_SUNID_Pos   22U

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position

Definition at line 3505 of file core_cm55.h.

◆ DIB_DAUTHSTATUS_SUNID_Msk [2/3]

#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask

Definition at line 3506 of file core_cm55.h.

◆ DIB_DAUTHSTATUS_SUID_Pos [2/3]

#define DIB_DAUTHSTATUS_SUID_Pos   20U

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position

Definition at line 3508 of file core_cm55.h.

◆ DIB_DAUTHSTATUS_SUID_Msk [2/3]

#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask

Definition at line 3509 of file core_cm55.h.

◆ DIB_DAUTHSTATUS_NSUNID_Pos [2/3]

#define DIB_DAUTHSTATUS_NSUNID_Pos   18U

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position

Definition at line 3511 of file core_cm55.h.

◆ DIB_DAUTHSTATUS_NSUNID_Msk [2/3]

#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask

Definition at line 3512 of file core_cm55.h.

◆ DIB_DAUTHSTATUS_NSUID_Pos [2/3]

#define DIB_DAUTHSTATUS_NSUID_Pos   16U

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position

Definition at line 3514 of file core_cm55.h.

◆ DIB_DAUTHSTATUS_NSUID_Msk [2/3]

#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask

Definition at line 3515 of file core_cm55.h.

◆ MEMSYSCTL_BASE [1/2]

#define MEMSYSCTL_BASE   (0xE001E000UL)

Memory System Control Base Address

Definition at line 3593 of file core_cm55.h.

◆ ERRBNK_BASE [1/2]

#define ERRBNK_BASE   (0xE001E100UL)

Error Banking Base Address

Definition at line 3594 of file core_cm55.h.

◆ PWRMODCTL_BASE [1/2]

#define PWRMODCTL_BASE   (0xE001E300UL)

Power Mode Control Base Address

Definition at line 3595 of file core_cm55.h.

◆ EWIC_BASE [1/2]

#define EWIC_BASE   (0xE001E400UL)

External Wakeup Interrupt Controller Base Address

Definition at line 3596 of file core_cm55.h.

◆ PRCCFGINF_BASE [1/2]

#define PRCCFGINF_BASE   (0xE001E700UL)

Processor Configuration Information Base Address

Definition at line 3597 of file core_cm55.h.

◆ ICB [1/2]

#define ICB   ((ICB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 3607 of file core_cm55.h.

◆ MEMSYSCTL [1/2]

#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )

Memory System Control configuration struct

Definition at line 3614 of file core_cm55.h.

◆ ERRBNK [1/2]

#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )

Error Banking configuration struct

Definition at line 3615 of file core_cm55.h.

◆ PWRMODCTL [1/2]

#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )

Power Mode Control configuration struct

Definition at line 3616 of file core_cm55.h.

◆ EWIC [1/2]

#define EWIC   ((EWIC_Type *) EWIC_BASE )

EWIC configuration struct

Definition at line 3617 of file core_cm55.h.

◆ PRCCFGINF [1/2]

#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )

Processor Configuration Information configuration struct

Definition at line 3618 of file core_cm55.h.

◆ SCnSCB_ACTLR_DISMCYCINT_Pos

#define SCnSCB_ACTLR_DISMCYCINT_Pos   0U

ACTLR: DISMCYCINT Position

Definition at line 472 of file core_sc000.h.

◆ SCnSCB_ACTLR_DISMCYCINT_Msk

#define SCnSCB_ACTLR_DISMCYCINT_Msk   (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

ACTLR: DISMCYCINT Mask

Definition at line 473 of file core_sc000.h.

◆ MPU_RBAR_ADDR_Pos [2/6]

#define MPU_RBAR_ADDR_Pos   8U

MPU RBAR: ADDR Position

Definition at line 574 of file core_sc000.h.

◆ MPU_RBAR_ADDR_Msk [2/6]

#define MPU_RBAR_ADDR_Msk   (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

Definition at line 575 of file core_sc000.h.

◆ MPU_RBAR_VALID_Pos [2/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

Definition at line 577 of file core_sc000.h.

◆ MPU_RBAR_VALID_Msk [2/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

Definition at line 578 of file core_sc000.h.

◆ MPU_RBAR_REGION_Pos [2/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

Definition at line 580 of file core_sc000.h.

◆ MPU_RBAR_REGION_Msk [2/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

Definition at line 581 of file core_sc000.h.

◆ MPU_RASR_ATTRS_Pos [2/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

Definition at line 584 of file core_sc000.h.

◆ MPU_RASR_ATTRS_Msk [2/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

Definition at line 585 of file core_sc000.h.

◆ MPU_RASR_XN_Pos [2/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

Definition at line 587 of file core_sc000.h.

◆ MPU_RASR_XN_Msk [2/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

Definition at line 588 of file core_sc000.h.

◆ MPU_RASR_AP_Pos [2/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

Definition at line 590 of file core_sc000.h.

◆ MPU_RASR_AP_Msk [2/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

Definition at line 591 of file core_sc000.h.

◆ MPU_RASR_TEX_Pos [2/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

Definition at line 593 of file core_sc000.h.

◆ MPU_RASR_TEX_Msk [2/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

Definition at line 594 of file core_sc000.h.

◆ MPU_RASR_S_Pos [2/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

Definition at line 596 of file core_sc000.h.

◆ MPU_RASR_S_Msk [2/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

Definition at line 597 of file core_sc000.h.

◆ MPU_RASR_C_Pos [2/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

Definition at line 599 of file core_sc000.h.

◆ MPU_RASR_C_Msk [2/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

Definition at line 600 of file core_sc000.h.

◆ MPU_RASR_B_Pos [2/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

Definition at line 602 of file core_sc000.h.

◆ MPU_RASR_B_Msk [2/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

Definition at line 603 of file core_sc000.h.

◆ MPU_RASR_SRD_Pos [2/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

Definition at line 605 of file core_sc000.h.

◆ MPU_RASR_SRD_Msk [2/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

Definition at line 606 of file core_sc000.h.

◆ MPU_RASR_SIZE_Pos [2/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

Definition at line 608 of file core_sc000.h.

◆ MPU_RASR_SIZE_Msk [2/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

Definition at line 609 of file core_sc000.h.

◆ MPU_RASR_ENABLE_Pos [2/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

Definition at line 611 of file core_sc000.h.

◆ MPU_RASR_ENABLE_Msk [2/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

Definition at line 612 of file core_sc000.h.

◆ TPI_ACPR_SWOSCALER_Pos [3/5]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 748 of file core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Msk [3/5]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 749 of file core_armv8mbl.h.

◆ TPI_PSCR_PSCount_Pos [3/5]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 779 of file core_armv8mbl.h.

◆ TPI_PSCR_PSCount_Msk [3/5]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 780 of file core_armv8mbl.h.

◆ TPI_LSR_nTT_Pos [3/5]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 783 of file core_armv8mbl.h.

◆ TPI_LSR_nTT_Msk [3/5]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 784 of file core_armv8mbl.h.

◆ TPI_LSR_SLK_Pos [3/5]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 786 of file core_armv8mbl.h.

◆ TPI_LSR_SLK_Msk [3/5]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 787 of file core_armv8mbl.h.

◆ TPI_LSR_SLI_Pos [3/5]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 789 of file core_armv8mbl.h.

◆ TPI_LSR_SLI_Msk [3/5]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 790 of file core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Pos [4/5]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 1324 of file core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Msk [4/5]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1325 of file core_armv8mml.h.

◆ TPI_PSCR_PSCount_Pos [4/5]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 1355 of file core_armv8mml.h.

◆ TPI_PSCR_PSCount_Msk [4/5]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1356 of file core_armv8mml.h.

◆ TPI_LSR_nTT_Pos [4/5]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1359 of file core_armv8mml.h.

◆ TPI_LSR_nTT_Msk [4/5]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1360 of file core_armv8mml.h.

◆ TPI_LSR_SLK_Pos [4/5]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 1362 of file core_armv8mml.h.

◆ TPI_LSR_SLK_Msk [4/5]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 1363 of file core_armv8mml.h.

◆ TPI_LSR_SLI_Pos [4/5]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 1365 of file core_armv8mml.h.

◆ TPI_LSR_SLI_Msk [4/5]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 1366 of file core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Pos [5/5]

#define TPI_ACPR_SWOSCALER_Pos   0U

TPI ACPR: SWOSCALER Position

Definition at line 1786 of file core_cm85.h.

◆ TPI_ACPR_SWOSCALER_Msk [5/5]

#define TPI_ACPR_SWOSCALER_Msk   (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1787 of file core_cm85.h.

◆ TPI_FFCR_EnFmt_Pos [3/3]

#define TPI_FFCR_EnFmt_Pos   0U

TPI FFCR: EnFmt Position

Definition at line 1813 of file core_cm85.h.

◆ TPI_FFCR_EnFmt_Msk [3/3]

#define TPI_FFCR_EnFmt_Msk   (0x3UL << /*TPI_FFCR_EnFmt_Pos*/)

TPI FFCR: EnFmt Mask

Definition at line 1814 of file core_cm85.h.

◆ TPI_PSCR_PSCount_Pos [5/5]

#define TPI_PSCR_PSCount_Pos   0U

TPI PSCR: PSCount Position

Definition at line 1817 of file core_cm85.h.

◆ TPI_PSCR_PSCount_Msk [5/5]

#define TPI_PSCR_PSCount_Msk   (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)

TPI PSCR: TPSCount Mask

Definition at line 1818 of file core_cm85.h.

◆ TPI_LSR_nTT_Pos [5/5]

#define TPI_LSR_nTT_Pos   1U

TPI LSR: Not thirty-two bit. Position

Definition at line 1821 of file core_cm85.h.

◆ TPI_LSR_nTT_Msk [5/5]

#define TPI_LSR_nTT_Msk   (0x1UL << TPI_LSR_nTT_Pos)

TPI LSR: Not thirty-two bit. Mask

Definition at line 1822 of file core_cm85.h.

◆ TPI_LSR_SLK_Pos [5/5]

#define TPI_LSR_SLK_Pos   1U

TPI LSR: Software Lock status Position

Definition at line 1824 of file core_cm85.h.

◆ TPI_LSR_SLK_Msk [5/5]

#define TPI_LSR_SLK_Msk   (0x1UL << TPI_LSR_SLK_Pos)

TPI LSR: Software Lock status Mask

Definition at line 1825 of file core_cm85.h.

◆ TPI_LSR_SLI_Pos [5/5]

#define TPI_LSR_SLI_Pos   0U

TPI LSR: Software Lock implemented Position

Definition at line 1827 of file core_cm85.h.

◆ TPI_LSR_SLI_Msk [5/5]

#define TPI_LSR_SLI_Msk   (0x1UL /*<< TPI_LSR_SLI_Pos*/)

TPI LSR: Software Lock implemented Mask

Definition at line 1828 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [3/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1006 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [3/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1007 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [3/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1057 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [3/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1058 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [3/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1060 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [3/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1061 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [3/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1063 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [3/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1064 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [3/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1066 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [3/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1067 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_CDS_Pos [3/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

Definition at line 1070 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_CDS_Msk [3/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

Definition at line 1071 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [3/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

Definition at line 1073 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [3/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

Definition at line 1074 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [3/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

Definition at line 1076 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [3/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1077 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [4/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1751 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [4/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1752 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [4/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1835 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [4/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1836 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [4/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1838 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [4/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1839 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [4/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1841 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [4/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1842 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [4/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1844 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [4/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1845 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_CDS_Pos [4/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

Definition at line 1848 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_CDS_Msk [4/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

Definition at line 1849 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [4/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

Definition at line 1851 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [4/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

Definition at line 1852 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [4/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

Definition at line 1854 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [4/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1855 of file core_armv8mml.h.

◆ MPU_RBAR_ADDR_Pos [3/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

Definition at line 1197 of file core_cm3.h.

◆ MPU_RBAR_ADDR_Msk [3/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

Definition at line 1198 of file core_cm3.h.

◆ MPU_RBAR_VALID_Pos [3/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

Definition at line 1200 of file core_cm3.h.

◆ MPU_RBAR_VALID_Msk [3/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

Definition at line 1201 of file core_cm3.h.

◆ MPU_RBAR_REGION_Pos [3/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

Definition at line 1203 of file core_cm3.h.

◆ MPU_RBAR_REGION_Msk [3/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

Definition at line 1204 of file core_cm3.h.

◆ MPU_RASR_ATTRS_Pos [3/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

Definition at line 1207 of file core_cm3.h.

◆ MPU_RASR_ATTRS_Msk [3/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

Definition at line 1208 of file core_cm3.h.

◆ MPU_RASR_XN_Pos [3/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

Definition at line 1210 of file core_cm3.h.

◆ MPU_RASR_XN_Msk [3/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

Definition at line 1211 of file core_cm3.h.

◆ MPU_RASR_AP_Pos [3/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

Definition at line 1213 of file core_cm3.h.

◆ MPU_RASR_AP_Msk [3/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

Definition at line 1214 of file core_cm3.h.

◆ MPU_RASR_TEX_Pos [3/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

Definition at line 1216 of file core_cm3.h.

◆ MPU_RASR_TEX_Msk [3/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

Definition at line 1217 of file core_cm3.h.

◆ MPU_RASR_S_Pos [3/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

Definition at line 1219 of file core_cm3.h.

◆ MPU_RASR_S_Msk [3/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

Definition at line 1220 of file core_cm3.h.

◆ MPU_RASR_C_Pos [3/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

Definition at line 1222 of file core_cm3.h.

◆ MPU_RASR_C_Msk [3/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

Definition at line 1223 of file core_cm3.h.

◆ MPU_RASR_B_Pos [3/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

Definition at line 1225 of file core_cm3.h.

◆ MPU_RASR_B_Msk [3/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

Definition at line 1226 of file core_cm3.h.

◆ MPU_RASR_SRD_Pos [3/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

Definition at line 1228 of file core_cm3.h.

◆ MPU_RASR_SRD_Msk [3/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

Definition at line 1229 of file core_cm3.h.

◆ MPU_RASR_SIZE_Pos [3/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

Definition at line 1231 of file core_cm3.h.

◆ MPU_RASR_SIZE_Msk [3/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

Definition at line 1232 of file core_cm3.h.

◆ MPU_RASR_ENABLE_Pos [3/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

Definition at line 1234 of file core_cm3.h.

◆ MPU_RASR_ENABLE_Msk [3/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

Definition at line 1235 of file core_cm3.h.

◆ MPU_RBAR_ADDR_Pos [4/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

Definition at line 1255 of file core_cm4.h.

◆ MPU_RBAR_ADDR_Msk [4/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

Definition at line 1256 of file core_cm4.h.

◆ MPU_RBAR_VALID_Pos [4/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

Definition at line 1258 of file core_cm4.h.

◆ MPU_RBAR_VALID_Msk [4/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

Definition at line 1259 of file core_cm4.h.

◆ MPU_RBAR_REGION_Pos [4/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

Definition at line 1261 of file core_cm4.h.

◆ MPU_RBAR_REGION_Msk [4/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

Definition at line 1262 of file core_cm4.h.

◆ MPU_RASR_ATTRS_Pos [4/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

Definition at line 1265 of file core_cm4.h.

◆ MPU_RASR_ATTRS_Msk [4/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

Definition at line 1266 of file core_cm4.h.

◆ MPU_RASR_XN_Pos [4/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

Definition at line 1268 of file core_cm4.h.

◆ MPU_RASR_XN_Msk [4/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

Definition at line 1269 of file core_cm4.h.

◆ MPU_RASR_AP_Pos [4/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

Definition at line 1271 of file core_cm4.h.

◆ MPU_RASR_AP_Msk [4/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

Definition at line 1272 of file core_cm4.h.

◆ MPU_RASR_TEX_Pos [4/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

Definition at line 1274 of file core_cm4.h.

◆ MPU_RASR_TEX_Msk [4/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

Definition at line 1275 of file core_cm4.h.

◆ MPU_RASR_S_Pos [4/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

Definition at line 1277 of file core_cm4.h.

◆ MPU_RASR_S_Msk [4/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

Definition at line 1278 of file core_cm4.h.

◆ MPU_RASR_C_Pos [4/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

Definition at line 1280 of file core_cm4.h.

◆ MPU_RASR_C_Msk [4/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

Definition at line 1281 of file core_cm4.h.

◆ MPU_RASR_B_Pos [4/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

Definition at line 1283 of file core_cm4.h.

◆ MPU_RASR_B_Msk [4/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

Definition at line 1284 of file core_cm4.h.

◆ MPU_RASR_SRD_Pos [4/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

Definition at line 1286 of file core_cm4.h.

◆ MPU_RASR_SRD_Msk [4/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

Definition at line 1287 of file core_cm4.h.

◆ MPU_RASR_SIZE_Pos [4/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

Definition at line 1289 of file core_cm4.h.

◆ MPU_RASR_SIZE_Msk [4/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

Definition at line 1290 of file core_cm4.h.

◆ MPU_RASR_ENABLE_Pos [4/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

Definition at line 1292 of file core_cm4.h.

◆ MPU_RASR_ENABLE_Msk [4/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

Definition at line 1293 of file core_cm4.h.

◆ MPU_RBAR_ADDR_Pos [5/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

Definition at line 1482 of file core_cm7.h.

◆ MPU_RBAR_ADDR_Msk [5/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

Definition at line 1483 of file core_cm7.h.

◆ MPU_RBAR_VALID_Pos [5/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

Definition at line 1485 of file core_cm7.h.

◆ MPU_RBAR_VALID_Msk [5/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

Definition at line 1486 of file core_cm7.h.

◆ MPU_RBAR_REGION_Pos [5/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

Definition at line 1488 of file core_cm7.h.

◆ MPU_RBAR_REGION_Msk [5/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

Definition at line 1489 of file core_cm7.h.

◆ MPU_RASR_ATTRS_Pos [5/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

Definition at line 1492 of file core_cm7.h.

◆ MPU_RASR_ATTRS_Msk [5/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

Definition at line 1493 of file core_cm7.h.

◆ MPU_RASR_XN_Pos [5/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

Definition at line 1495 of file core_cm7.h.

◆ MPU_RASR_XN_Msk [5/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

Definition at line 1496 of file core_cm7.h.

◆ MPU_RASR_AP_Pos [5/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

Definition at line 1498 of file core_cm7.h.

◆ MPU_RASR_AP_Msk [5/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

Definition at line 1499 of file core_cm7.h.

◆ MPU_RASR_TEX_Pos [5/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

Definition at line 1501 of file core_cm7.h.

◆ MPU_RASR_TEX_Msk [5/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

Definition at line 1502 of file core_cm7.h.

◆ MPU_RASR_S_Pos [5/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

Definition at line 1504 of file core_cm7.h.

◆ MPU_RASR_S_Msk [5/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

Definition at line 1505 of file core_cm7.h.

◆ MPU_RASR_C_Pos [5/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

Definition at line 1507 of file core_cm7.h.

◆ MPU_RASR_C_Msk [5/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

Definition at line 1508 of file core_cm7.h.

◆ MPU_RASR_B_Pos [5/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

Definition at line 1510 of file core_cm7.h.

◆ MPU_RASR_B_Msk [5/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

Definition at line 1511 of file core_cm7.h.

◆ MPU_RASR_SRD_Pos [5/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

Definition at line 1513 of file core_cm7.h.

◆ MPU_RASR_SRD_Msk [5/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

Definition at line 1514 of file core_cm7.h.

◆ MPU_RASR_SIZE_Pos [5/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

Definition at line 1516 of file core_cm7.h.

◆ MPU_RASR_SIZE_Msk [5/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

Definition at line 1517 of file core_cm7.h.

◆ MPU_RASR_ENABLE_Pos [5/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

Definition at line 1519 of file core_cm7.h.

◆ MPU_RASR_ENABLE_Msk [5/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

Definition at line 1520 of file core_cm7.h.

◆ MPU_RLAR_PXN_Pos [3/3]

#define MPU_RLAR_PXN_Pos   4U

MPU RLAR: PXN Position

Definition at line 2747 of file core_cm85.h.

◆ MPU_RLAR_PXN_Msk [3/3]

#define MPU_RLAR_PXN_Msk   (1UL << MPU_RLAR_PXN_Pos)

MPU RLAR: PXN Mask

Definition at line 2748 of file core_cm85.h.

◆ MPU_RBAR_ADDR_Pos [6/6]

#define MPU_RBAR_ADDR_Pos   5U

MPU RBAR: ADDR Position

Definition at line 1180 of file core_sc300.h.

◆ MPU_RBAR_ADDR_Msk [6/6]

#define MPU_RBAR_ADDR_Msk   (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)

MPU RBAR: ADDR Mask

Definition at line 1181 of file core_sc300.h.

◆ MPU_RBAR_VALID_Pos [6/6]

#define MPU_RBAR_VALID_Pos   4U

MPU RBAR: VALID Position

Definition at line 1183 of file core_sc300.h.

◆ MPU_RBAR_VALID_Msk [6/6]

#define MPU_RBAR_VALID_Msk   (1UL << MPU_RBAR_VALID_Pos)

MPU RBAR: VALID Mask

Definition at line 1184 of file core_sc300.h.

◆ MPU_RBAR_REGION_Pos [6/6]

#define MPU_RBAR_REGION_Pos   0U

MPU RBAR: REGION Position

Definition at line 1186 of file core_sc300.h.

◆ MPU_RBAR_REGION_Msk [6/6]

#define MPU_RBAR_REGION_Msk   (0xFUL /*<< MPU_RBAR_REGION_Pos*/)

MPU RBAR: REGION Mask

Definition at line 1187 of file core_sc300.h.

◆ MPU_RASR_ATTRS_Pos [6/6]

#define MPU_RASR_ATTRS_Pos   16U

MPU RASR: MPU Region Attribute field Position

Definition at line 1190 of file core_sc300.h.

◆ MPU_RASR_ATTRS_Msk [6/6]

#define MPU_RASR_ATTRS_Msk   (0xFFFFUL << MPU_RASR_ATTRS_Pos)

MPU RASR: MPU Region Attribute field Mask

Definition at line 1191 of file core_sc300.h.

◆ MPU_RASR_XN_Pos [6/6]

#define MPU_RASR_XN_Pos   28U

MPU RASR: ATTRS.XN Position

Definition at line 1193 of file core_sc300.h.

◆ MPU_RASR_XN_Msk [6/6]

#define MPU_RASR_XN_Msk   (1UL << MPU_RASR_XN_Pos)

MPU RASR: ATTRS.XN Mask

Definition at line 1194 of file core_sc300.h.

◆ MPU_RASR_AP_Pos [6/6]

#define MPU_RASR_AP_Pos   24U

MPU RASR: ATTRS.AP Position

Definition at line 1196 of file core_sc300.h.

◆ MPU_RASR_AP_Msk [6/6]

#define MPU_RASR_AP_Msk   (0x7UL << MPU_RASR_AP_Pos)

MPU RASR: ATTRS.AP Mask

Definition at line 1197 of file core_sc300.h.

◆ MPU_RASR_TEX_Pos [6/6]

#define MPU_RASR_TEX_Pos   19U

MPU RASR: ATTRS.TEX Position

Definition at line 1199 of file core_sc300.h.

◆ MPU_RASR_TEX_Msk [6/6]

#define MPU_RASR_TEX_Msk   (0x7UL << MPU_RASR_TEX_Pos)

MPU RASR: ATTRS.TEX Mask

Definition at line 1200 of file core_sc300.h.

◆ MPU_RASR_S_Pos [6/6]

#define MPU_RASR_S_Pos   18U

MPU RASR: ATTRS.S Position

Definition at line 1202 of file core_sc300.h.

◆ MPU_RASR_S_Msk [6/6]

#define MPU_RASR_S_Msk   (1UL << MPU_RASR_S_Pos)

MPU RASR: ATTRS.S Mask

Definition at line 1203 of file core_sc300.h.

◆ MPU_RASR_C_Pos [6/6]

#define MPU_RASR_C_Pos   17U

MPU RASR: ATTRS.C Position

Definition at line 1205 of file core_sc300.h.

◆ MPU_RASR_C_Msk [6/6]

#define MPU_RASR_C_Msk   (1UL << MPU_RASR_C_Pos)

MPU RASR: ATTRS.C Mask

Definition at line 1206 of file core_sc300.h.

◆ MPU_RASR_B_Pos [6/6]

#define MPU_RASR_B_Pos   16U

MPU RASR: ATTRS.B Position

Definition at line 1208 of file core_sc300.h.

◆ MPU_RASR_B_Msk [6/6]

#define MPU_RASR_B_Msk   (1UL << MPU_RASR_B_Pos)

MPU RASR: ATTRS.B Mask

Definition at line 1209 of file core_sc300.h.

◆ MPU_RASR_SRD_Pos [6/6]

#define MPU_RASR_SRD_Pos   8U

MPU RASR: Sub-Region Disable Position

Definition at line 1211 of file core_sc300.h.

◆ MPU_RASR_SRD_Msk [6/6]

#define MPU_RASR_SRD_Msk   (0xFFUL << MPU_RASR_SRD_Pos)

MPU RASR: Sub-Region Disable Mask

Definition at line 1212 of file core_sc300.h.

◆ MPU_RASR_SIZE_Pos [6/6]

#define MPU_RASR_SIZE_Pos   1U

MPU RASR: Region Size Field Position

Definition at line 1214 of file core_sc300.h.

◆ MPU_RASR_SIZE_Msk [6/6]

#define MPU_RASR_SIZE_Msk   (0x1FUL << MPU_RASR_SIZE_Pos)

MPU RASR: Region Size Field Mask

Definition at line 1215 of file core_sc300.h.

◆ MPU_RASR_ENABLE_Pos [6/6]

#define MPU_RASR_ENABLE_Pos   0U

MPU RASR: Region enable bit Position

Definition at line 1217 of file core_sc300.h.

◆ MPU_RASR_ENABLE_Msk [6/6]

#define MPU_RASR_ENABLE_Msk   (1UL /*<< MPU_RASR_ENABLE_Pos*/)

MPU RASR: Region enable bit Disable Mask

Definition at line 1218 of file core_sc300.h.

◆ FPU_FPDSCR_FZ16_Pos [3/3]

#define FPU_FPDSCR_FZ16_Pos   19U

FPDSCR: FZ16 bit Position

Definition at line 2963 of file core_cm85.h.

◆ FPU_FPDSCR_FZ16_Msk [3/3]

#define FPU_FPDSCR_FZ16_Msk   (1UL << FPU_FPDSCR_FZ16_Pos)

FPDSCR: FZ16 bit Mask

Definition at line 2964 of file core_cm85.h.

◆ FPU_FPDSCR_LTPSIZE_Pos [3/3]

#define FPU_FPDSCR_LTPSIZE_Pos   16U

FPDSCR: LTPSIZE bit Position

Definition at line 2966 of file core_cm85.h.

◆ FPU_FPDSCR_LTPSIZE_Msk [3/3]

#define FPU_FPDSCR_LTPSIZE_Msk   (7UL << FPU_FPDSCR_LTPSIZE_Pos)

FPDSCR: LTPSIZE bit Mask

Definition at line 2967 of file core_cm85.h.

◆ FPU_MVFR0_FPRound_Pos [3/3]

#define FPU_MVFR0_FPRound_Pos   28U

MVFR0: FPRound bits Position

Definition at line 2970 of file core_cm85.h.

◆ FPU_MVFR0_FPRound_Msk [3/3]

#define FPU_MVFR0_FPRound_Msk   (0xFUL << FPU_MVFR0_FPRound_Pos)

MVFR0: FPRound bits Mask

Definition at line 2971 of file core_cm85.h.

◆ FPU_MVFR0_FPSqrt_Pos [3/3]

#define FPU_MVFR0_FPSqrt_Pos   20U

MVFR0: FPSqrt bits Position

Definition at line 2973 of file core_cm85.h.

◆ FPU_MVFR0_FPSqrt_Msk [3/3]

#define FPU_MVFR0_FPSqrt_Msk   (0xFUL << FPU_MVFR0_FPSqrt_Pos)

MVFR0: FPSqrt bits Mask

Definition at line 2974 of file core_cm85.h.

◆ FPU_MVFR0_FPDivide_Pos [3/3]

#define FPU_MVFR0_FPDivide_Pos   16U

MVFR0: FPDivide bits Position

Definition at line 2976 of file core_cm85.h.

◆ FPU_MVFR0_FPDivide_Msk [3/3]

#define FPU_MVFR0_FPDivide_Msk   (0xFUL << FPU_MVFR0_FPDivide_Pos)

MVFR0: Divide bits Mask

Definition at line 2977 of file core_cm85.h.

◆ FPU_MVFR0_FPDP_Pos [3/3]

#define FPU_MVFR0_FPDP_Pos   8U

MVFR0: FPDP bits Position

Definition at line 2979 of file core_cm85.h.

◆ FPU_MVFR0_FPDP_Msk [3/3]

#define FPU_MVFR0_FPDP_Msk   (0xFUL << FPU_MVFR0_FPDP_Pos)

MVFR0: FPDP bits Mask

Definition at line 2980 of file core_cm85.h.

◆ FPU_MVFR0_FPSP_Pos [3/3]

#define FPU_MVFR0_FPSP_Pos   4U

MVFR0: FPSP bits Position

Definition at line 2982 of file core_cm85.h.

◆ FPU_MVFR0_FPSP_Msk [3/3]

#define FPU_MVFR0_FPSP_Msk   (0xFUL << FPU_MVFR0_FPSP_Pos)

MVFR0: FPSP bits Mask

Definition at line 2983 of file core_cm85.h.

◆ FPU_MVFR0_SIMDReg_Pos [3/3]

#define FPU_MVFR0_SIMDReg_Pos   0U

MVFR0: SIMDReg bits Position

Definition at line 2985 of file core_cm85.h.

◆ FPU_MVFR0_SIMDReg_Msk [3/3]

#define FPU_MVFR0_SIMDReg_Msk   (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/)

MVFR0: SIMDReg bits Mask

Definition at line 2986 of file core_cm85.h.

◆ FPU_MVFR1_FMAC_Pos [3/3]

#define FPU_MVFR1_FMAC_Pos   28U

MVFR1: FMAC bits Position

Definition at line 2989 of file core_cm85.h.

◆ FPU_MVFR1_FMAC_Msk [3/3]

#define FPU_MVFR1_FMAC_Msk   (0xFUL << FPU_MVFR1_FMAC_Pos)

MVFR1: FMAC bits Mask

Definition at line 2990 of file core_cm85.h.

◆ FPU_MVFR1_FPHP_Pos [3/3]

#define FPU_MVFR1_FPHP_Pos   24U

MVFR1: FPHP bits Position

Definition at line 2992 of file core_cm85.h.

◆ FPU_MVFR1_FPHP_Msk [3/3]

#define FPU_MVFR1_FPHP_Msk   (0xFUL << FPU_MVFR1_FPHP_Pos)

MVFR1: FPHP bits Mask

Definition at line 2993 of file core_cm85.h.

◆ FPU_MVFR1_FP16_Pos [3/3]

#define FPU_MVFR1_FP16_Pos   20U

MVFR1: FP16 bits Position

Definition at line 2995 of file core_cm85.h.

◆ FPU_MVFR1_FP16_Msk [3/3]

#define FPU_MVFR1_FP16_Msk   (0xFUL << FPU_MVFR1_FP16_Pos)

MVFR1: FP16 bits Mask

Definition at line 2996 of file core_cm85.h.

◆ FPU_MVFR1_MVE_Pos [3/3]

#define FPU_MVFR1_MVE_Pos   8U

MVFR1: MVE bits Position

Definition at line 2998 of file core_cm85.h.

◆ FPU_MVFR1_MVE_Msk [3/3]

#define FPU_MVFR1_MVE_Msk   (0xFUL << FPU_MVFR1_MVE_Pos)

MVFR1: MVE bits Mask

Definition at line 2999 of file core_cm85.h.

◆ FPU_MVFR1_FPDNaN_Pos [3/3]

#define FPU_MVFR1_FPDNaN_Pos   4U

MVFR1: FPDNaN bits Position

Definition at line 3001 of file core_cm85.h.

◆ FPU_MVFR1_FPDNaN_Msk [3/3]

#define FPU_MVFR1_FPDNaN_Msk   (0xFUL << FPU_MVFR1_FPDNaN_Pos)

MVFR1: FPDNaN bits Mask

Definition at line 3002 of file core_cm85.h.

◆ FPU_MVFR1_FPFtZ_Pos [3/3]

#define FPU_MVFR1_FPFtZ_Pos   0U

MVFR1: FPFtZ bits Position

Definition at line 3004 of file core_cm85.h.

◆ FPU_MVFR1_FPFtZ_Msk [3/3]

#define FPU_MVFR1_FPFtZ_Msk   (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/)

MVFR1: FPFtZ bits Mask

Definition at line 3005 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [5/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1081 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [5/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1082 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [5/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1132 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [5/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1133 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [5/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1135 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [5/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1136 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [5/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1138 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [5/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1139 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [5/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1141 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [5/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1142 of file core_cm23.h.

◆ CoreDebug_DSCSR_CDS_Pos [5/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

Definition at line 1145 of file core_cm23.h.

◆ CoreDebug_DSCSR_CDS_Msk [5/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

Definition at line 1146 of file core_cm23.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [5/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

Definition at line 1148 of file core_cm23.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [5/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

Definition at line 1149 of file core_cm23.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [5/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

Definition at line 1151 of file core_cm23.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [5/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1152 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [6/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1826 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [6/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1827 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [6/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1910 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [6/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1911 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [6/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1913 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [6/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1914 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [6/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1916 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [6/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1917 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [6/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1919 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [6/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1920 of file core_cm33.h.

◆ CoreDebug_DSCSR_CDS_Pos [6/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

Definition at line 1923 of file core_cm33.h.

◆ CoreDebug_DSCSR_CDS_Msk [6/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

Definition at line 1924 of file core_cm33.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [6/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

Definition at line 1926 of file core_cm33.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [6/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

Definition at line 1927 of file core_cm33.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [6/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

Definition at line 1929 of file core_cm33.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [6/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1930 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [7/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1826 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [7/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1827 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [7/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1910 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [7/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1911 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [7/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1913 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [7/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1914 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [7/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1916 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [7/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1917 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [7/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1919 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [7/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1920 of file core_cm35p.h.

◆ CoreDebug_DSCSR_CDS_Pos [7/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position
Deprecated
CoreDebug DSCSR: CDS Position

Definition at line 1923 of file core_cm35p.h.

◆ CoreDebug_DSCSR_CDS_Msk [7/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask
Deprecated
CoreDebug DSCSR: CDS Mask

Definition at line 1924 of file core_cm35p.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [7/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position
Deprecated
CoreDebug DSCSR: SBRSEL Position

Definition at line 1926 of file core_cm35p.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [7/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask
Deprecated
CoreDebug DSCSR: SBRSEL Mask

Definition at line 1927 of file core_cm35p.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [7/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position
Deprecated
CoreDebug DSCSR: SBRSELEN Position

Definition at line 1929 of file core_cm35p.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [7/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1930 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [8/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U
Deprecated
CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 3039 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [8/8]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
Deprecated
CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 3040 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_FPD_Pos [3/3]

#define CoreDebug_DHCSR_S_FPD_Pos   23U
Deprecated
CoreDebug DHCSR: S_FPD Position

Definition at line 3048 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_FPD_Msk [3/3]

#define CoreDebug_DHCSR_S_FPD_Msk   (1UL << CoreDebug_DHCSR_S_FPD_Pos)
Deprecated
CoreDebug DHCSR: S_FPD Mask

Definition at line 3049 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_SUIDE_Pos [3/3]

#define CoreDebug_DHCSR_S_SUIDE_Pos   22U
Deprecated
CoreDebug DHCSR: S_SUIDE Position

Definition at line 3051 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_SUIDE_Msk [3/3]

#define CoreDebug_DHCSR_S_SUIDE_Msk   (1UL << CoreDebug_DHCSR_S_SUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_SUIDE Mask

Definition at line 3052 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_NSUIDE_Pos [3/3]

#define CoreDebug_DHCSR_S_NSUIDE_Pos   21U
Deprecated
CoreDebug DHCSR: S_NSUIDE Position

Definition at line 3054 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_NSUIDE_Msk [3/3]

#define CoreDebug_DHCSR_S_NSUIDE_Msk   (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos)
Deprecated
CoreDebug DHCSR: S_NSUIDE Mask

Definition at line 3055 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_SDE_Pos [3/3]

#define CoreDebug_DHCSR_S_SDE_Pos   20U
Deprecated
CoreDebug DHCSR: S_SDE Position

Definition at line 3057 of file core_cm85.h.

◆ CoreDebug_DHCSR_S_SDE_Msk [3/3]

#define CoreDebug_DHCSR_S_SDE_Msk   (1UL << CoreDebug_DHCSR_S_SDE_Pos)
Deprecated
CoreDebug DHCSR: S_SDE Mask

Definition at line 3058 of file core_cm85.h.

◆ CoreDebug_DHCSR_C_PMOV_Pos [3/3]

#define CoreDebug_DHCSR_C_PMOV_Pos   6U
Deprecated
CoreDebug DHCSR: C_PMOV Position

Definition at line 3072 of file core_cm85.h.

◆ CoreDebug_DHCSR_C_PMOV_Msk [3/3]

#define CoreDebug_DHCSR_C_PMOV_Msk   (1UL << CoreDebug_DHCSR_C_PMOV_Pos)
Deprecated
CoreDebug DHCSR: C_PMOV Mask

Definition at line 3073 of file core_cm85.h.

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Pos [3/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos   19U
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Position

Definition at line 3138 of file core_cm85.h.

◆ CoreDebug_DSCEMCR_CLR_MON_REQ_Msk [3/3]

#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_REQ, Mask

Definition at line 3139 of file core_cm85.h.

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Pos [3/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos   17U
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Position

Definition at line 3141 of file core_cm85.h.

◆ CoreDebug_DSCEMCR_CLR_MON_PEND_Msk [3/3]

#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: CLR_MON_PEND, Mask

Definition at line 3142 of file core_cm85.h.

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Pos [3/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos   3U
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Position

Definition at line 3144 of file core_cm85.h.

◆ CoreDebug_DSCEMCR_SET_MON_REQ_Msk [3/3]

#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_REQ, Mask

Definition at line 3145 of file core_cm85.h.

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Pos [3/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos   1U
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Position

Definition at line 3147 of file core_cm85.h.

◆ CoreDebug_DSCEMCR_SET_MON_PEND_Msk [3/3]

#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk   (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos)
Deprecated
CoreDebug DSCEMCR: SET_MON_PEND, Mask

Definition at line 3148 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_UIDEN_Pos [3/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Pos   10U
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Position

Definition at line 3151 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_UIDEN_Msk [3/3]

#define CoreDebug_DAUTHCTRL_UIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDEN, Mask

Definition at line 3152 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Pos [3/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos   9U
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Position

Definition at line 3154 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_UIDAPEN_Msk [3/3]

#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk   (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: UIDAPEN, Mask

Definition at line 3155 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_FSDMA_Pos [3/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Pos   8U
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Position

Definition at line 3157 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_FSDMA_Msk [3/3]

#define CoreDebug_DAUTHCTRL_FSDMA_Msk   (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos)
Deprecated
CoreDebug DAUTHCTRL: FSDMA, Mask

Definition at line 3158 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [8/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos   3U
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 3160 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [8/8]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 3161 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [8/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos   2U
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 3163 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [8/8]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk   (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
Deprecated
CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 3164 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [8/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 3166 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [8/8]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk   (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
Deprecated
CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 3167 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [8/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 3169 of file core_cm85.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [8/8]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk   (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
Deprecated
CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 3170 of file core_cm85.h.

◆ CoreDebug_DSCSR_CDS_Pos [8/8]

#define CoreDebug_DSCSR_CDS_Pos   16U
Deprecated
CoreDebug DSCSR: CDS Position

Definition at line 3173 of file core_cm85.h.

◆ CoreDebug_DSCSR_CDS_Msk [8/8]

#define CoreDebug_DSCSR_CDS_Msk   (1UL << CoreDebug_DSCSR_CDS_Pos)
Deprecated
CoreDebug DSCSR: CDS Mask

Definition at line 3174 of file core_cm85.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [8/8]

#define CoreDebug_DSCSR_SBRSEL_Pos   1U
Deprecated
CoreDebug DSCSR: SBRSEL Position

Definition at line 3176 of file core_cm85.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [8/8]

#define CoreDebug_DSCSR_SBRSEL_Msk   (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
Deprecated
CoreDebug DSCSR: SBRSEL Mask

Definition at line 3177 of file core_cm85.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [8/8]

#define CoreDebug_DSCSR_SBRSELEN_Pos   0U
Deprecated
CoreDebug DSCSR: SBRSELEN Position

Definition at line 3179 of file core_cm85.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [8/8]

#define CoreDebug_DSCSR_SBRSELEN_Msk   (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
Deprecated
CoreDebug DSCSR: SBRSELEN Mask

Definition at line 3180 of file core_cm85.h.

◆ DCB_DHCSR_S_FPD_Pos [3/3]

#define DCB_DHCSR_S_FPD_Pos   23U

DCB DHCSR: Floating-point registers Debuggable Position

Definition at line 3219 of file core_cm85.h.

◆ DCB_DHCSR_S_FPD_Msk [3/3]

#define DCB_DHCSR_S_FPD_Msk   (0x1UL << DCB_DHCSR_S_FPD_Pos)

DCB DHCSR: Floating-point registers Debuggable Mask

Definition at line 3220 of file core_cm85.h.

◆ DCB_DHCSR_S_SUIDE_Pos [3/3]

#define DCB_DHCSR_S_SUIDE_Pos   22U

DCB DHCSR: Secure unprivileged halting debug enabled Position

Definition at line 3222 of file core_cm85.h.

◆ DCB_DHCSR_S_SUIDE_Msk [3/3]

#define DCB_DHCSR_S_SUIDE_Msk   (0x1UL << DCB_DHCSR_S_SUIDE_Pos)

DCB DHCSR: Secure unprivileged halting debug enabled Mask

Definition at line 3223 of file core_cm85.h.

◆ DCB_DHCSR_S_NSUIDE_Pos [3/3]

#define DCB_DHCSR_S_NSUIDE_Pos   21U

DCB DHCSR: Non-secure unprivileged halting debug enabled Position

Definition at line 3225 of file core_cm85.h.

◆ DCB_DHCSR_S_NSUIDE_Msk [3/3]

#define DCB_DHCSR_S_NSUIDE_Msk   (0x1UL << DCB_DHCSR_S_NSUIDE_Pos)

DCB DHCSR: Non-secure unprivileged halting debug enabled Mask

Definition at line 3226 of file core_cm85.h.

◆ DCB_DHCSR_C_PMOV_Pos [3/3]

#define DCB_DHCSR_C_PMOV_Pos   6U

DCB DHCSR: Halt on PMU overflow control Position

Definition at line 3243 of file core_cm85.h.

◆ DCB_DHCSR_C_PMOV_Msk [3/3]

#define DCB_DHCSR_C_PMOV_Msk   (0x1UL << DCB_DHCSR_C_PMOV_Pos)

DCB DHCSR: Halt on PMU overflow control Mask

Definition at line 3244 of file core_cm85.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Pos [3/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Pos   19U

DCB DSCEMCR: Clear monitor request Position

Definition at line 3325 of file core_cm85.h.

◆ DCB_DSCEMCR_CLR_MON_REQ_Msk [3/3]

#define DCB_DSCEMCR_CLR_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos)

DCB DSCEMCR: Clear monitor request Mask

Definition at line 3326 of file core_cm85.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Pos [3/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Pos   17U

DCB DSCEMCR: Clear monitor pend Position

Definition at line 3328 of file core_cm85.h.

◆ DCB_DSCEMCR_CLR_MON_PEND_Msk [3/3]

#define DCB_DSCEMCR_CLR_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos)

DCB DSCEMCR: Clear monitor pend Mask

Definition at line 3329 of file core_cm85.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Pos [3/3]

#define DCB_DSCEMCR_SET_MON_REQ_Pos   3U

DCB DSCEMCR: Set monitor request Position

Definition at line 3331 of file core_cm85.h.

◆ DCB_DSCEMCR_SET_MON_REQ_Msk [3/3]

#define DCB_DSCEMCR_SET_MON_REQ_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos)

DCB DSCEMCR: Set monitor request Mask

Definition at line 3332 of file core_cm85.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Pos [3/3]

#define DCB_DSCEMCR_SET_MON_PEND_Pos   1U

DCB DSCEMCR: Set monitor pend Position

Definition at line 3334 of file core_cm85.h.

◆ DCB_DSCEMCR_SET_MON_PEND_Msk [3/3]

#define DCB_DSCEMCR_SET_MON_PEND_Msk   (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos)

DCB DSCEMCR: Set monitor pend Mask

Definition at line 3335 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDEN_Pos [3/3]

#define DCB_DAUTHCTRL_UIDEN_Pos   10U

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position

Definition at line 3338 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDEN_Msk [3/3]

#define DCB_DAUTHCTRL_UIDEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask

Definition at line 3339 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Pos [3/3]

#define DCB_DAUTHCTRL_UIDAPEN_Pos   9U

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position

Definition at line 3341 of file core_cm85.h.

◆ DCB_DAUTHCTRL_UIDAPEN_Msk [3/3]

#define DCB_DAUTHCTRL_UIDAPEN_Msk   (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos)

DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask

Definition at line 3342 of file core_cm85.h.

◆ DCB_DAUTHCTRL_FSDMA_Pos [3/3]

#define DCB_DAUTHCTRL_FSDMA_Pos   8U

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position

Definition at line 3344 of file core_cm85.h.

◆ DCB_DAUTHCTRL_FSDMA_Msk [3/3]

#define DCB_DAUTHCTRL_FSDMA_Msk   (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos)

DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask

Definition at line 3345 of file core_cm85.h.

◆ DIB_DAUTHSTATUS_SUNID_Pos [3/3]

#define DIB_DAUTHSTATUS_SUNID_Pos   22U

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position

Definition at line 3410 of file core_cm85.h.

◆ DIB_DAUTHSTATUS_SUNID_Msk [3/3]

#define DIB_DAUTHSTATUS_SUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask

Definition at line 3411 of file core_cm85.h.

◆ DIB_DAUTHSTATUS_SUID_Pos [3/3]

#define DIB_DAUTHSTATUS_SUID_Pos   20U

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position

Definition at line 3413 of file core_cm85.h.

◆ DIB_DAUTHSTATUS_SUID_Msk [3/3]

#define DIB_DAUTHSTATUS_SUID_Msk   (0x3UL << DIB_DAUTHSTATUS_SUID_Pos )

DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask

Definition at line 3414 of file core_cm85.h.

◆ DIB_DAUTHSTATUS_NSUNID_Pos [3/3]

#define DIB_DAUTHSTATUS_NSUNID_Pos   18U

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position

Definition at line 3416 of file core_cm85.h.

◆ DIB_DAUTHSTATUS_NSUNID_Msk [3/3]

#define DIB_DAUTHSTATUS_NSUNID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask

Definition at line 3417 of file core_cm85.h.

◆ DIB_DAUTHSTATUS_NSUID_Pos [3/3]

#define DIB_DAUTHSTATUS_NSUID_Pos   16U

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position

Definition at line 3419 of file core_cm85.h.

◆ DIB_DAUTHSTATUS_NSUID_Msk [3/3]

#define DIB_DAUTHSTATUS_NSUID_Msk   (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos )

DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask

Definition at line 3420 of file core_cm85.h.

◆ MEMSYSCTL_BASE [2/2]

#define MEMSYSCTL_BASE   (0xE001E000UL)

Memory System Control Base Address

Definition at line 3498 of file core_cm85.h.

◆ ERRBNK_BASE [2/2]

#define ERRBNK_BASE   (0xE001E100UL)

Error Banking Base Address

Definition at line 3499 of file core_cm85.h.

◆ PWRMODCTL_BASE [2/2]

#define PWRMODCTL_BASE   (0xE001E300UL)

Power Mode Control Base Address

Definition at line 3500 of file core_cm85.h.

◆ EWIC_BASE [2/2]

#define EWIC_BASE   (0xE001E400UL)

External Wakeup Interrupt Controller Base Address

Definition at line 3501 of file core_cm85.h.

◆ PRCCFGINF_BASE [2/2]

#define PRCCFGINF_BASE   (0xE001E700UL)

Processor Configuration Information Base Address

Definition at line 3502 of file core_cm85.h.

◆ ICB [2/2]

#define ICB   ((ICB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 3511 of file core_cm85.h.

◆ MEMSYSCTL [2/2]

#define MEMSYSCTL   ((MemSysCtl_Type *) MEMSYSCTL_BASE )

Memory System Control configuration struct

Definition at line 3518 of file core_cm85.h.

◆ ERRBNK [2/2]

#define ERRBNK   ((ErrBnk_Type *) ERRBNK_BASE )

Error Banking configuration struct

Definition at line 3519 of file core_cm85.h.

◆ PWRMODCTL [2/2]

#define PWRMODCTL   ((PwrModCtl_Type *) PWRMODCTL_BASE )

Power Mode Control configuration struct

Definition at line 3520 of file core_cm85.h.

◆ EWIC [2/2]

#define EWIC   ((EWIC_Type *) EWIC_BASE )

EWIC configuration struct

Definition at line 3521 of file core_cm85.h.

◆ PRCCFGINF [2/2]

#define PRCCFGINF   ((PrcCfgInf_Type *) PRCCFGINF_BASE )

Processor Configuration Information configuration struct

Definition at line 3522 of file core_cm85.h.

◆ ICB_ACTLR_DISCRITAXIRUW_Pos [2/2]

#define ICB_ACTLR_DISCRITAXIRUW_Pos   27U

ACTLR: DISCRITAXIRUW Position

Definition at line 1029 of file core_cm85.h.

◆ ICB_ACTLR_DISCRITAXIRUW_Msk [2/2]

#define ICB_ACTLR_DISCRITAXIRUW_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos)

ACTLR: DISCRITAXIRUW Mask

Definition at line 1030 of file core_cm85.h.

◆ ICB_ACTLR_DISCRITAXIRUR_Pos [2/2]

#define ICB_ACTLR_DISCRITAXIRUR_Pos   15U

ACTLR: DISCRITAXIRUR Position

Definition at line 1032 of file core_cm85.h.

◆ ICB_ACTLR_DISCRITAXIRUR_Msk [2/2]

#define ICB_ACTLR_DISCRITAXIRUR_Msk   (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos)

ACTLR: DISCRITAXIRUR Mask

Definition at line 1033 of file core_cm85.h.

◆ ICB_ACTLR_EVENTBUSEN_Pos [2/2]

#define ICB_ACTLR_EVENTBUSEN_Pos   14U

ACTLR: EVENTBUSEN Position

Definition at line 1035 of file core_cm85.h.

◆ ICB_ACTLR_EVENTBUSEN_Msk [2/2]

#define ICB_ACTLR_EVENTBUSEN_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_Pos)

ACTLR: EVENTBUSEN Mask

Definition at line 1036 of file core_cm85.h.

◆ ICB_ACTLR_EVENTBUSEN_S_Pos [2/2]

#define ICB_ACTLR_EVENTBUSEN_S_Pos   13U

ACTLR: EVENTBUSEN_S Position

Definition at line 1038 of file core_cm85.h.

◆ ICB_ACTLR_EVENTBUSEN_S_Msk [2/2]

#define ICB_ACTLR_EVENTBUSEN_S_Msk   (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos)

ACTLR: EVENTBUSEN_S Mask

Definition at line 1039 of file core_cm85.h.

◆ ICB_ACTLR_DISITMATBFLUSH_Pos [2/2]

#define ICB_ACTLR_DISITMATBFLUSH_Pos   12U

ACTLR: DISITMATBFLUSH Position

Definition at line 1041 of file core_cm85.h.

◆ ICB_ACTLR_DISITMATBFLUSH_Msk [2/2]

#define ICB_ACTLR_DISITMATBFLUSH_Msk   (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos)

ACTLR: DISITMATBFLUSH Mask

Definition at line 1042 of file core_cm85.h.

◆ ICB_ACTLR_DISNWAMODE_Pos [2/2]

#define ICB_ACTLR_DISNWAMODE_Pos   11U

ACTLR: DISNWAMODE Position

Definition at line 1044 of file core_cm85.h.

◆ ICB_ACTLR_DISNWAMODE_Msk [2/2]

#define ICB_ACTLR_DISNWAMODE_Msk   (1UL << ICB_ACTLR_DISNWAMODE_Pos)

ACTLR: DISNWAMODE Mask

Definition at line 1045 of file core_cm85.h.

◆ ICB_ACTLR_FPEXCODIS_Pos [2/2]

#define ICB_ACTLR_FPEXCODIS_Pos   10U

ACTLR: FPEXCODIS Position

Definition at line 1047 of file core_cm85.h.

◆ ICB_ACTLR_FPEXCODIS_Msk [2/2]

#define ICB_ACTLR_FPEXCODIS_Msk   (1UL << ICB_ACTLR_FPEXCODIS_Pos)

ACTLR: FPEXCODIS Mask

Definition at line 1048 of file core_cm85.h.

◆ ICB_ICTR_INTLINESNUM_Pos [2/2]

#define ICB_ICTR_INTLINESNUM_Pos   0U

ICTR: INTLINESNUM Position

Definition at line 1051 of file core_cm85.h.

◆ ICB_ICTR_INTLINESNUM_Msk [2/2]

#define ICB_ICTR_INTLINESNUM_Msk   (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 1052 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Pos [2/2]

#define MEMSYSCTL_MSCR_CPWRDN_Pos   17U

MEMSYSCTL MSCR: CPWRDN Position

Definition at line 1427 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_CPWRDN_Msk [2/2]

#define MEMSYSCTL_MSCR_CPWRDN_Msk   (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos)

MEMSYSCTL MSCR: CPWRDN Mask

Definition at line 1428 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Pos [2/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Pos   16U

MEMSYSCTL MSCR: DCCLEAN Position

Definition at line 1430 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCCLEAN_Msk [2/2]

#define MEMSYSCTL_MSCR_DCCLEAN_Msk   (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos)

MEMSYSCTL MSCR: DCCLEAN Mask

Definition at line 1431 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Pos [2/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Pos   13U

MEMSYSCTL MSCR: ICACTIVE Position

Definition at line 1433 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ICACTIVE_Msk [2/2]

#define MEMSYSCTL_MSCR_ICACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos)

MEMSYSCTL MSCR: ICACTIVE Mask

Definition at line 1434 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Pos [2/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Pos   12U

MEMSYSCTL MSCR: DCACTIVE Position

Definition at line 1436 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_DCACTIVE_Msk [2/2]

#define MEMSYSCTL_MSCR_DCACTIVE_Msk   (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos)

MEMSYSCTL MSCR: DCACTIVE Mask

Definition at line 1437 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Pos [2/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Pos   3U

MEMSYSCTL MSCR: EVECCFAULT Position

Definition at line 1439 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_EVECCFAULT_Msk [2/2]

#define MEMSYSCTL_MSCR_EVECCFAULT_Msk   (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos)

MEMSYSCTL MSCR: EVECCFAULT Mask

Definition at line 1440 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Pos [2/2]

#define MEMSYSCTL_MSCR_FORCEWT_Pos   2U

MEMSYSCTL MSCR: FORCEWT Position

Definition at line 1442 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_FORCEWT_Msk [2/2]

#define MEMSYSCTL_MSCR_FORCEWT_Msk   (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos)

MEMSYSCTL MSCR: FORCEWT Mask

Definition at line 1443 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ECCEN_Pos [2/2]

#define MEMSYSCTL_MSCR_ECCEN_Pos   1U

MEMSYSCTL MSCR: ECCEN Position

Definition at line 1445 of file core_cm85.h.

◆ MEMSYSCTL_MSCR_ECCEN_Msk [2/2]

#define MEMSYSCTL_MSCR_ECCEN_Msk   (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos)

MEMSYSCTL MSCR: ECCEN Mask

Definition at line 1446 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_DIS_NLP_Pos

#define MEMSYSCTL_PFCR_DIS_NLP_Pos   7U

MEMSYSCTL PFCR: DIS_NLP Position

Definition at line 1449 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_DIS_NLP_Msk

#define MEMSYSCTL_PFCR_DIS_NLP_Msk   (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos)

MEMSYSCTL PFCR: DIS_NLP Mask

Definition at line 1450 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_ENABLE_Pos [2/2]

#define MEMSYSCTL_PFCR_ENABLE_Pos   0U

MEMSYSCTL PFCR: ENABLE Position

Definition at line 1452 of file core_cm85.h.

◆ MEMSYSCTL_PFCR_ENABLE_Msk [2/2]

#define MEMSYSCTL_PFCR_ENABLE_Msk   (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/)

MEMSYSCTL PFCR: ENABLE Mask

Definition at line 1453 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_SZ_Pos [2/2]

#define MEMSYSCTL_ITCMCR_SZ_Pos   3U

MEMSYSCTL ITCMCR: SZ Position

Definition at line 1456 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_SZ_Msk [2/2]

#define MEMSYSCTL_ITCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos)

MEMSYSCTL ITCMCR: SZ Mask

Definition at line 1457 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_EN_Pos [2/2]

#define MEMSYSCTL_ITCMCR_EN_Pos   0U

MEMSYSCTL ITCMCR: EN Position

Definition at line 1459 of file core_cm85.h.

◆ MEMSYSCTL_ITCMCR_EN_Msk [2/2]

#define MEMSYSCTL_ITCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/)

MEMSYSCTL ITCMCR: EN Mask

Definition at line 1460 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_SZ_Pos [2/2]

#define MEMSYSCTL_DTCMCR_SZ_Pos   3U

MEMSYSCTL DTCMCR: SZ Position

Definition at line 1463 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_SZ_Msk [2/2]

#define MEMSYSCTL_DTCMCR_SZ_Msk   (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos)

MEMSYSCTL DTCMCR: SZ Mask

Definition at line 1464 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_EN_Pos [2/2]

#define MEMSYSCTL_DTCMCR_EN_Pos   0U

MEMSYSCTL DTCMCR: EN Position

Definition at line 1466 of file core_cm85.h.

◆ MEMSYSCTL_DTCMCR_EN_Msk [2/2]

#define MEMSYSCTL_DTCMCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/)

MEMSYSCTL DTCMCR: EN Mask

Definition at line 1467 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_SZ_Pos [2/2]

#define MEMSYSCTL_PAHBCR_SZ_Pos   1U

MEMSYSCTL PAHBCR: SZ Position

Definition at line 1470 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_SZ_Msk [2/2]

#define MEMSYSCTL_PAHBCR_SZ_Msk   (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos)

MEMSYSCTL PAHBCR: SZ Mask

Definition at line 1471 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_EN_Pos [2/2]

#define MEMSYSCTL_PAHBCR_EN_Pos   0U

MEMSYSCTL PAHBCR: EN Position

Definition at line 1473 of file core_cm85.h.

◆ MEMSYSCTL_PAHBCR_EN_Msk [2/2]

#define MEMSYSCTL_PAHBCR_EN_Msk   (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/)

MEMSYSCTL PAHBCR: EN Mask

Definition at line 1474 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Pos [2/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos   1U

MEMSYSCTL ITGU_CTRL: DEREN Position

Definition at line 1477 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DEREN_Msk [2/2]

#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos)

MEMSYSCTL ITGU_CTRL: DEREN Mask

Definition at line 1478 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Pos [2/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL ITGU_CTRL: DBFEN Position

Definition at line 1480 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CTRL_DBFEN_Msk [2/2]

#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL ITGU_CTRL: DBFEN Mask

Definition at line 1481 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos   31U

MEMSYSCTL ITGU_CFG: PRESENT Position

Definition at line 1484 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_PRESENT_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos)

MEMSYSCTL ITGU_CFG: PRESENT Mask

Definition at line 1485 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL ITGU_CFG: NUMBLKS Position

Definition at line 1487 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos)

MEMSYSCTL ITGU_CFG: NUMBLKS Mask

Definition at line 1488 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Pos [2/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL ITGU_CFG: BLKSZ Position

Definition at line 1490 of file core_cm85.h.

◆ MEMSYSCTL_ITGU_CFG_BLKSZ_Msk [2/2]

#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL ITGU_CFG: BLKSZ Mask

Definition at line 1491 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Pos [2/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos   1U

MEMSYSCTL DTGU_CTRL: DEREN Position

Definition at line 1494 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DEREN_Msk [2/2]

#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk   (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos)

MEMSYSCTL DTGU_CTRL: DEREN Mask

Definition at line 1495 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Pos [2/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos   0U

MEMSYSCTL DTGU_CTRL: DBFEN Position

Definition at line 1497 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CTRL_DBFEN_Msk [2/2]

#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk   (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/)

MEMSYSCTL DTGU_CTRL: DBFEN Mask

Definition at line 1498 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos   31U

MEMSYSCTL DTGU_CFG: PRESENT Position

Definition at line 1501 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_PRESENT_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk   (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos)

MEMSYSCTL DTGU_CFG: PRESENT Mask

Definition at line 1502 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos   8U

MEMSYSCTL DTGU_CFG: NUMBLKS Position

Definition at line 1504 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk   (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos)

MEMSYSCTL DTGU_CFG: NUMBLKS Mask

Definition at line 1505 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Pos [2/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos   0U

MEMSYSCTL DTGU_CFG: BLKSZ Position

Definition at line 1507 of file core_cm85.h.

◆ MEMSYSCTL_DTGU_CFG_BLKSZ_Msk [2/2]

#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk   (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/)

MEMSYSCTL DTGU_CFG: BLKSZ Mask

Definition at line 1508 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos [2/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos   8U

PWRMODCTL CPDLPSTATE: RLPSTATE Position

Definition at line 1531 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk [2/2]

#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos)

PWRMODCTL CPDLPSTATE: RLPSTATE Mask

Definition at line 1532 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos [2/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos   4U

PWRMODCTL CPDLPSTATE: ELPSTATE Position

Definition at line 1534 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk [2/2]

#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk   (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos)

PWRMODCTL CPDLPSTATE: ELPSTATE Mask

Definition at line 1535 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos [2/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos   0U

PWRMODCTL CPDLPSTATE: CLPSTATE Position

Definition at line 1537 of file core_cm85.h.

◆ PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk [2/2]

#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/)

PWRMODCTL CPDLPSTATE: CLPSTATE Mask

Definition at line 1538 of file core_cm85.h.

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos [2/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos   0U

PWRMODCTL DPDLPSTATE: DLPSTATE Position

Definition at line 1541 of file core_cm85.h.

◆ PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk [2/2]

#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk   (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/)

PWRMODCTL DPDLPSTATE: DLPSTATE Mask

Definition at line 1542 of file core_cm85.h.

◆ EWIC_EVENTSPR_EDBGREQ_Pos [2/2]

#define EWIC_EVENTSPR_EDBGREQ_Pos   2U

EWIC EVENTSPR: EDBGREQ Position

Definition at line 1566 of file core_cm85.h.

◆ EWIC_EVENTSPR_EDBGREQ_Msk [2/2]

#define EWIC_EVENTSPR_EDBGREQ_Msk   (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos)

EWIC EVENTSPR: EDBGREQ Mask

Definition at line 1567 of file core_cm85.h.

◆ EWIC_EVENTSPR_NMI_Pos [2/2]

#define EWIC_EVENTSPR_NMI_Pos   1U

EWIC EVENTSPR: NMI Position

Definition at line 1569 of file core_cm85.h.

◆ EWIC_EVENTSPR_NMI_Msk [2/2]

#define EWIC_EVENTSPR_NMI_Msk   (0x1UL << EWIC_EVENTSPR_NMI_Pos)

EWIC EVENTSPR: NMI Mask

Definition at line 1570 of file core_cm85.h.

◆ EWIC_EVENTSPR_EVENT_Pos [2/2]

#define EWIC_EVENTSPR_EVENT_Pos   0U

EWIC EVENTSPR: EVENT Position

Definition at line 1572 of file core_cm85.h.

◆ EWIC_EVENTSPR_EVENT_Msk [2/2]

#define EWIC_EVENTSPR_EVENT_Msk   (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/)

EWIC EVENTSPR: EVENT Mask

Definition at line 1573 of file core_cm85.h.

◆ EWIC_EVENTMASKA_EDBGREQ_Pos [2/2]

#define EWIC_EVENTMASKA_EDBGREQ_Pos   2U

EWIC EVENTMASKA: EDBGREQ Position

Definition at line 1576 of file core_cm85.h.

◆ EWIC_EVENTMASKA_EDBGREQ_Msk [2/2]

#define EWIC_EVENTMASKA_EDBGREQ_Msk   (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos)

EWIC EVENTMASKA: EDBGREQ Mask

Definition at line 1577 of file core_cm85.h.

◆ EWIC_EVENTMASKA_NMI_Pos [2/2]

#define EWIC_EVENTMASKA_NMI_Pos   1U

EWIC EVENTMASKA: NMI Position

Definition at line 1579 of file core_cm85.h.

◆ EWIC_EVENTMASKA_NMI_Msk [2/2]

#define EWIC_EVENTMASKA_NMI_Msk   (0x1UL << EWIC_EVENTMASKA_NMI_Pos)

EWIC EVENTMASKA: NMI Mask

Definition at line 1580 of file core_cm85.h.

◆ EWIC_EVENTMASKA_EVENT_Pos [2/2]

#define EWIC_EVENTMASKA_EVENT_Pos   0U

EWIC EVENTMASKA: EVENT Position

Definition at line 1582 of file core_cm85.h.

◆ EWIC_EVENTMASKA_EVENT_Msk [2/2]

#define EWIC_EVENTMASKA_EVENT_Msk   (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/)

EWIC EVENTMASKA: EVENT Mask

Definition at line 1583 of file core_cm85.h.

◆ EWIC_EVENTMASK_IRQ_Pos [2/2]

#define EWIC_EVENTMASK_IRQ_Pos   0U

EWIC EVENTMASKA: IRQ Position

Definition at line 1586 of file core_cm85.h.

◆ EWIC_EVENTMASK_IRQ_Msk [2/2]

#define EWIC_EVENTMASK_IRQ_Msk   (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/)

EWIC EVENTMASKA: IRQ Mask

Definition at line 1587 of file core_cm85.h.

◆ ERRBNK_IEBR0_SWDEF_Pos [2/2]

#define ERRBNK_IEBR0_SWDEF_Pos   30U

ERRBNK IEBR0: SWDEF Position

Definition at line 1616 of file core_cm85.h.

◆ ERRBNK_IEBR0_SWDEF_Msk [2/2]

#define ERRBNK_IEBR0_SWDEF_Msk   (0x3UL << ERRBNK_IEBR0_SWDEF_Pos)

ERRBNK IEBR0: SWDEF Mask

Definition at line 1617 of file core_cm85.h.

◆ ERRBNK_IEBR0_BANK_Pos [2/2]

#define ERRBNK_IEBR0_BANK_Pos   16U

ERRBNK IEBR0: BANK Position

Definition at line 1619 of file core_cm85.h.

◆ ERRBNK_IEBR0_BANK_Msk [2/2]

#define ERRBNK_IEBR0_BANK_Msk   (0x1UL << ERRBNK_IEBR0_BANK_Pos)

ERRBNK IEBR0: BANK Mask

Definition at line 1620 of file core_cm85.h.

◆ ERRBNK_IEBR0_LOCATION_Pos [2/2]

#define ERRBNK_IEBR0_LOCATION_Pos   2U

ERRBNK IEBR0: LOCATION Position

Definition at line 1622 of file core_cm85.h.

◆ ERRBNK_IEBR0_LOCATION_Msk [2/2]

#define ERRBNK_IEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos)

ERRBNK IEBR0: LOCATION Mask

Definition at line 1623 of file core_cm85.h.

◆ ERRBNK_IEBR0_LOCKED_Pos [2/2]

#define ERRBNK_IEBR0_LOCKED_Pos   1U

ERRBNK IEBR0: LOCKED Position

Definition at line 1625 of file core_cm85.h.

◆ ERRBNK_IEBR0_LOCKED_Msk [2/2]

#define ERRBNK_IEBR0_LOCKED_Msk   (0x1UL << ERRBNK_IEBR0_LOCKED_Pos)

ERRBNK IEBR0: LOCKED Mask

Definition at line 1626 of file core_cm85.h.

◆ ERRBNK_IEBR0_VALID_Pos [2/2]

#define ERRBNK_IEBR0_VALID_Pos   0U

ERRBNK IEBR0: VALID Position

Definition at line 1628 of file core_cm85.h.

◆ ERRBNK_IEBR0_VALID_Msk [2/2]

#define ERRBNK_IEBR0_VALID_Msk   (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/)

ERRBNK IEBR0: VALID Mask

Definition at line 1629 of file core_cm85.h.

◆ ERRBNK_IEBR1_SWDEF_Pos [2/2]

#define ERRBNK_IEBR1_SWDEF_Pos   30U

ERRBNK IEBR1: SWDEF Position

Definition at line 1632 of file core_cm85.h.

◆ ERRBNK_IEBR1_SWDEF_Msk [2/2]

#define ERRBNK_IEBR1_SWDEF_Msk   (0x3UL << ERRBNK_IEBR1_SWDEF_Pos)

ERRBNK IEBR1: SWDEF Mask

Definition at line 1633 of file core_cm85.h.

◆ ERRBNK_IEBR1_BANK_Pos [2/2]

#define ERRBNK_IEBR1_BANK_Pos   16U

ERRBNK IEBR1: BANK Position

Definition at line 1635 of file core_cm85.h.

◆ ERRBNK_IEBR1_BANK_Msk [2/2]

#define ERRBNK_IEBR1_BANK_Msk   (0x1UL << ERRBNK_IEBR1_BANK_Pos)

ERRBNK IEBR1: BANK Mask

Definition at line 1636 of file core_cm85.h.

◆ ERRBNK_IEBR1_LOCATION_Pos [2/2]

#define ERRBNK_IEBR1_LOCATION_Pos   2U

ERRBNK IEBR1: LOCATION Position

Definition at line 1638 of file core_cm85.h.

◆ ERRBNK_IEBR1_LOCATION_Msk [2/2]

#define ERRBNK_IEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos)

ERRBNK IEBR1: LOCATION Mask

Definition at line 1639 of file core_cm85.h.

◆ ERRBNK_IEBR1_LOCKED_Pos [2/2]

#define ERRBNK_IEBR1_LOCKED_Pos   1U

ERRBNK IEBR1: LOCKED Position

Definition at line 1641 of file core_cm85.h.

◆ ERRBNK_IEBR1_LOCKED_Msk [2/2]

#define ERRBNK_IEBR1_LOCKED_Msk   (0x1UL << ERRBNK_IEBR1_LOCKED_Pos)

ERRBNK IEBR1: LOCKED Mask

Definition at line 1642 of file core_cm85.h.

◆ ERRBNK_IEBR1_VALID_Pos [2/2]

#define ERRBNK_IEBR1_VALID_Pos   0U

ERRBNK IEBR1: VALID Position

Definition at line 1644 of file core_cm85.h.

◆ ERRBNK_IEBR1_VALID_Msk [2/2]

#define ERRBNK_IEBR1_VALID_Msk   (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/)

ERRBNK IEBR1: VALID Mask

Definition at line 1645 of file core_cm85.h.

◆ ERRBNK_DEBR0_SWDEF_Pos [2/2]

#define ERRBNK_DEBR0_SWDEF_Pos   30U

ERRBNK DEBR0: SWDEF Position

Definition at line 1648 of file core_cm85.h.

◆ ERRBNK_DEBR0_SWDEF_Msk [2/2]

#define ERRBNK_DEBR0_SWDEF_Msk   (0x3UL << ERRBNK_DEBR0_SWDEF_Pos)

ERRBNK DEBR0: SWDEF Mask

Definition at line 1649 of file core_cm85.h.

◆ ERRBNK_DEBR0_TYPE_Pos [2/2]

#define ERRBNK_DEBR0_TYPE_Pos   17U

ERRBNK DEBR0: TYPE Position

Definition at line 1651 of file core_cm85.h.

◆ ERRBNK_DEBR0_TYPE_Msk [2/2]

#define ERRBNK_DEBR0_TYPE_Msk   (0x1UL << ERRBNK_DEBR0_TYPE_Pos)

ERRBNK DEBR0: TYPE Mask

Definition at line 1652 of file core_cm85.h.

◆ ERRBNK_DEBR0_BANK_Pos [2/2]

#define ERRBNK_DEBR0_BANK_Pos   16U

ERRBNK DEBR0: BANK Position

Definition at line 1654 of file core_cm85.h.

◆ ERRBNK_DEBR0_BANK_Msk [2/2]

#define ERRBNK_DEBR0_BANK_Msk   (0x1UL << ERRBNK_DEBR0_BANK_Pos)

ERRBNK DEBR0: BANK Mask

Definition at line 1655 of file core_cm85.h.

◆ ERRBNK_DEBR0_LOCATION_Pos [2/2]

#define ERRBNK_DEBR0_LOCATION_Pos   2U

ERRBNK DEBR0: LOCATION Position

Definition at line 1657 of file core_cm85.h.

◆ ERRBNK_DEBR0_LOCATION_Msk [2/2]

#define ERRBNK_DEBR0_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos)

ERRBNK DEBR0: LOCATION Mask

Definition at line 1658 of file core_cm85.h.

◆ ERRBNK_DEBR0_LOCKED_Pos [2/2]

#define ERRBNK_DEBR0_LOCKED_Pos   1U

ERRBNK DEBR0: LOCKED Position

Definition at line 1660 of file core_cm85.h.

◆ ERRBNK_DEBR0_LOCKED_Msk [2/2]

#define ERRBNK_DEBR0_LOCKED_Msk   (0x1UL << ERRBNK_DEBR0_LOCKED_Pos)

ERRBNK DEBR0: LOCKED Mask

Definition at line 1661 of file core_cm85.h.

◆ ERRBNK_DEBR0_VALID_Pos [2/2]

#define ERRBNK_DEBR0_VALID_Pos   0U

ERRBNK DEBR0: VALID Position

Definition at line 1663 of file core_cm85.h.

◆ ERRBNK_DEBR0_VALID_Msk [2/2]

#define ERRBNK_DEBR0_VALID_Msk   (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/)

ERRBNK DEBR0: VALID Mask

Definition at line 1664 of file core_cm85.h.

◆ ERRBNK_DEBR1_SWDEF_Pos [2/2]

#define ERRBNK_DEBR1_SWDEF_Pos   30U

ERRBNK DEBR1: SWDEF Position

Definition at line 1667 of file core_cm85.h.

◆ ERRBNK_DEBR1_SWDEF_Msk [2/2]

#define ERRBNK_DEBR1_SWDEF_Msk   (0x3UL << ERRBNK_DEBR1_SWDEF_Pos)

ERRBNK DEBR1: SWDEF Mask

Definition at line 1668 of file core_cm85.h.

◆ ERRBNK_DEBR1_TYPE_Pos [2/2]

#define ERRBNK_DEBR1_TYPE_Pos   17U

ERRBNK DEBR1: TYPE Position

Definition at line 1670 of file core_cm85.h.

◆ ERRBNK_DEBR1_TYPE_Msk [2/2]

#define ERRBNK_DEBR1_TYPE_Msk   (0x1UL << ERRBNK_DEBR1_TYPE_Pos)

ERRBNK DEBR1: TYPE Mask

Definition at line 1671 of file core_cm85.h.

◆ ERRBNK_DEBR1_BANK_Pos [2/2]

#define ERRBNK_DEBR1_BANK_Pos   16U

ERRBNK DEBR1: BANK Position

Definition at line 1673 of file core_cm85.h.

◆ ERRBNK_DEBR1_BANK_Msk [2/2]

#define ERRBNK_DEBR1_BANK_Msk   (0x1UL << ERRBNK_DEBR1_BANK_Pos)

ERRBNK DEBR1: BANK Mask

Definition at line 1674 of file core_cm85.h.

◆ ERRBNK_DEBR1_LOCATION_Pos [2/2]

#define ERRBNK_DEBR1_LOCATION_Pos   2U

ERRBNK DEBR1: LOCATION Position

Definition at line 1676 of file core_cm85.h.

◆ ERRBNK_DEBR1_LOCATION_Msk [2/2]

#define ERRBNK_DEBR1_LOCATION_Msk   (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos)

ERRBNK DEBR1: LOCATION Mask

Definition at line 1677 of file core_cm85.h.

◆ ERRBNK_DEBR1_LOCKED_Pos [2/2]

#define ERRBNK_DEBR1_LOCKED_Pos   1U

ERRBNK DEBR1: LOCKED Position

Definition at line 1679 of file core_cm85.h.

◆ ERRBNK_DEBR1_LOCKED_Msk [2/2]

#define ERRBNK_DEBR1_LOCKED_Msk   (0x1UL << ERRBNK_DEBR1_LOCKED_Pos)

ERRBNK DEBR1: LOCKED Mask

Definition at line 1680 of file core_cm85.h.

◆ ERRBNK_DEBR1_VALID_Pos [2/2]

#define ERRBNK_DEBR1_VALID_Pos   0U

ERRBNK DEBR1: VALID Position

Definition at line 1682 of file core_cm85.h.

◆ ERRBNK_DEBR1_VALID_Msk [2/2]

#define ERRBNK_DEBR1_VALID_Msk   (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/)

ERRBNK DEBR1: VALID Mask

Definition at line 1683 of file core_cm85.h.

◆ ERRBNK_TEBR0_SWDEF_Pos [2/2]

#define ERRBNK_TEBR0_SWDEF_Pos   30U

ERRBNK TEBR0: SWDEF Position

Definition at line 1686 of file core_cm85.h.

◆ ERRBNK_TEBR0_SWDEF_Msk [2/2]

#define ERRBNK_TEBR0_SWDEF_Msk   (0x3UL << ERRBNK_TEBR0_SWDEF_Pos)

ERRBNK TEBR0: SWDEF Mask

Definition at line 1687 of file core_cm85.h.

◆ ERRBNK_TEBR0_POISON_Pos [2/2]

#define ERRBNK_TEBR0_POISON_Pos   28U

ERRBNK TEBR0: POISON Position

Definition at line 1689 of file core_cm85.h.

◆ ERRBNK_TEBR0_POISON_Msk [2/2]

#define ERRBNK_TEBR0_POISON_Msk   (0x1UL << ERRBNK_TEBR0_POISON_Pos)

ERRBNK TEBR0: POISON Mask

Definition at line 1690 of file core_cm85.h.

◆ ERRBNK_TEBR0_TYPE_Pos [2/2]

#define ERRBNK_TEBR0_TYPE_Pos   27U

ERRBNK TEBR0: TYPE Position

Definition at line 1692 of file core_cm85.h.

◆ ERRBNK_TEBR0_TYPE_Msk [2/2]

#define ERRBNK_TEBR0_TYPE_Msk   (0x1UL << ERRBNK_TEBR0_TYPE_Pos)

ERRBNK TEBR0: TYPE Mask

Definition at line 1693 of file core_cm85.h.

◆ ERRBNK_TEBR0_BANK_Pos [2/2]

#define ERRBNK_TEBR0_BANK_Pos   24U

ERRBNK TEBR0: BANK Position

Definition at line 1695 of file core_cm85.h.

◆ ERRBNK_TEBR0_BANK_Msk [2/2]

#define ERRBNK_TEBR0_BANK_Msk   (0x3UL << ERRBNK_TEBR0_BANK_Pos)

ERRBNK TEBR0: BANK Mask

Definition at line 1696 of file core_cm85.h.

◆ ERRBNK_TEBR0_LOCATION_Pos [2/2]

#define ERRBNK_TEBR0_LOCATION_Pos   2U

ERRBNK TEBR0: LOCATION Position

Definition at line 1698 of file core_cm85.h.

◆ ERRBNK_TEBR0_LOCATION_Msk [2/2]

#define ERRBNK_TEBR0_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos)

ERRBNK TEBR0: LOCATION Mask

Definition at line 1699 of file core_cm85.h.

◆ ERRBNK_TEBR0_LOCKED_Pos [2/2]

#define ERRBNK_TEBR0_LOCKED_Pos   1U

ERRBNK TEBR0: LOCKED Position

Definition at line 1701 of file core_cm85.h.

◆ ERRBNK_TEBR0_LOCKED_Msk [2/2]

#define ERRBNK_TEBR0_LOCKED_Msk   (0x1UL << ERRBNK_TEBR0_LOCKED_Pos)

ERRBNK TEBR0: LOCKED Mask

Definition at line 1702 of file core_cm85.h.

◆ ERRBNK_TEBR0_VALID_Pos [2/2]

#define ERRBNK_TEBR0_VALID_Pos   0U

ERRBNK TEBR0: VALID Position

Definition at line 1704 of file core_cm85.h.

◆ ERRBNK_TEBR0_VALID_Msk [2/2]

#define ERRBNK_TEBR0_VALID_Msk   (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/)

ERRBNK TEBR0: VALID Mask

Definition at line 1705 of file core_cm85.h.

◆ ERRBNK_TEBR1_SWDEF_Pos [2/2]

#define ERRBNK_TEBR1_SWDEF_Pos   30U

ERRBNK TEBR1: SWDEF Position

Definition at line 1708 of file core_cm85.h.

◆ ERRBNK_TEBR1_SWDEF_Msk [2/2]

#define ERRBNK_TEBR1_SWDEF_Msk   (0x3UL << ERRBNK_TEBR1_SWDEF_Pos)

ERRBNK TEBR1: SWDEF Mask

Definition at line 1709 of file core_cm85.h.

◆ ERRBNK_TEBR1_POISON_Pos [2/2]

#define ERRBNK_TEBR1_POISON_Pos   28U

ERRBNK TEBR1: POISON Position

Definition at line 1711 of file core_cm85.h.

◆ ERRBNK_TEBR1_POISON_Msk [2/2]

#define ERRBNK_TEBR1_POISON_Msk   (0x1UL << ERRBNK_TEBR1_POISON_Pos)

ERRBNK TEBR1: POISON Mask

Definition at line 1712 of file core_cm85.h.

◆ ERRBNK_TEBR1_TYPE_Pos [2/2]

#define ERRBNK_TEBR1_TYPE_Pos   27U

ERRBNK TEBR1: TYPE Position

Definition at line 1714 of file core_cm85.h.

◆ ERRBNK_TEBR1_TYPE_Msk [2/2]

#define ERRBNK_TEBR1_TYPE_Msk   (0x1UL << ERRBNK_TEBR1_TYPE_Pos)

ERRBNK TEBR1: TYPE Mask

Definition at line 1715 of file core_cm85.h.

◆ ERRBNK_TEBR1_BANK_Pos [2/2]

#define ERRBNK_TEBR1_BANK_Pos   24U

ERRBNK TEBR1: BANK Position

Definition at line 1717 of file core_cm85.h.

◆ ERRBNK_TEBR1_BANK_Msk [2/2]

#define ERRBNK_TEBR1_BANK_Msk   (0x3UL << ERRBNK_TEBR1_BANK_Pos)

ERRBNK TEBR1: BANK Mask

Definition at line 1718 of file core_cm85.h.

◆ ERRBNK_TEBR1_LOCATION_Pos [2/2]

#define ERRBNK_TEBR1_LOCATION_Pos   2U

ERRBNK TEBR1: LOCATION Position

Definition at line 1720 of file core_cm85.h.

◆ ERRBNK_TEBR1_LOCATION_Msk [2/2]

#define ERRBNK_TEBR1_LOCATION_Msk   (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos)

ERRBNK TEBR1: LOCATION Mask

Definition at line 1721 of file core_cm85.h.

◆ ERRBNK_TEBR1_LOCKED_Pos [2/2]

#define ERRBNK_TEBR1_LOCKED_Pos   1U

ERRBNK TEBR1: LOCKED Position

Definition at line 1723 of file core_cm85.h.

◆ ERRBNK_TEBR1_LOCKED_Msk [2/2]

#define ERRBNK_TEBR1_LOCKED_Msk   (0x1UL << ERRBNK_TEBR1_LOCKED_Pos)

ERRBNK TEBR1: LOCKED Mask

Definition at line 1724 of file core_cm85.h.

◆ ERRBNK_TEBR1_VALID_Pos [2/2]

#define ERRBNK_TEBR1_VALID_Pos   0U

ERRBNK TEBR1: VALID Position

Definition at line 1726 of file core_cm85.h.

◆ ERRBNK_TEBR1_VALID_Msk [2/2]

#define ERRBNK_TEBR1_VALID_Msk   (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/)

ERRBNK TEBR1: VALID Mask

Definition at line 1727 of file core_cm85.h.